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Change subject: /: Update and rewrite README.md
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File README.md:
https://review.coreboot.org/c/coreboot/+/67119/comment/2ed2a5ab_fb33ac52
PS3, Line 30: T
what is the meaning of this "T"? 😊
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for
dynamic table switching support.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8
---
M src/soc/amd/mendocino/root_complex.c
1 file changed, 154 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68649/11
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
Expand DPTC_INPUT macro to supoort 16 DPTC thermal table parameters for
dynamic table switching support.
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---
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Change subject: cpu: Add SPDX license headers to Makefiles
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
I Don't have an opinion on hash sign, but one empty line after SPDX line, makes it look more eye-appealing
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Change subject: soc/intel/meteorlake: Implement SOC Die lock down configuration
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68430/comment/f1aad6bf_50a95104
PS2, Line 13: Able to build and boot rex to OS.
would appreciate if you can add a more specific test line apart from just booting to OS.
I guess the S0ix is what being blocked without this CL?
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Change subject: soc/amd/mendocino: Enable x86 SHA accelerator
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/mendocino/Kconfig:
https://review.coreboot.org/c/coreboot/+/68954/comment/68ed1779_a7ab138e
PS1, Line 101: select VBOOT_X86_SHA256_ACCELERATION
if VBOOT
Otherwise non-google boards such as `AMD_CHAUSIE` would fail.
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Change subject: security/vboot: Update build rules using x86 SHA extension
......................................................................
Patch Set 1:
(1 comment)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68953/comment/7638f52b_ea8bf811
PS1, Line 26: ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
> I think `ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)` […]
Actually, the help text of `VBOOT_X86_SHA256_ACCELERATION` says `Use sha extension for sha256 hash calculation`, so maybe we should put the logic in the Kconfig, instead of modifying Makefile.inc here.
```
select VBOOT_X86_SHA256_ACCELERATION if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK
```
Also, the dependency of `VBOOT_X86_SHA256_ACCELERATION` can also be changed to `ARCH_VERSTAGE_X86_32 || ARCH_VERSTAGE_X86_64`.
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Change subject: drivers/ocp/dmi: Fix smbios type 11 get wrong ppin value for second socket
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68910/comment/194c00dc_4c6ea1bb
PS3, Line 10: Due to cpu index and cpu logic number may be different after cpu init,
: this may cause the wrong smbios type 11 ppin value for second socket.
:
: Here uses cpu index to get apic id first and then get the logic cpu
: which is on second socket. With this way, can get ppin value from
: second socket.
> The xeon_sp numa code should not change the struct device lapic_id as it confused the cpu init code. […]
With function from CB:68912, can check if the cpu comes from second socket directly. Thanks.
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Change subject: cpu: Add SPDX license headers to Makefiles
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS2:
Generally
File src/cpu/amd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68979/comment/bcdab8cb_ebfad143
PS1, Line 1: ## SPDX-License-Identifier: GPL-2.0-only
nit: I think these files could use one empty line after SPDX comment to make them more eye-appealing
https://review.coreboot.org/c/coreboot/+/68979/comment/df5eebd1_33badd3a
PS1, Line 1: ##
One hash sign should be enough. Also applies to all other Makefiles
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