coreboot-gerrit October 2022

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[M] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
by Jan Samek (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Angel Pons, Werner Zeh. Jan Samek has uploaded a new patch set (#2) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M ...................................................................... mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases (like this one - emiting POST codes through a PCIe device). For the inicialization to happen properly, certain register writes specified in Apollo Lake IAFW vol. 2 (#559811), chapter 3.3.1, have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emited before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/bootblock.c 1 file changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68223/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache
by Reka Norman (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Subrata Banik, Reka Norman, Nick Vaccaro, Julius Werner, Angel Pons, Karthikeyan Ramasubramanian. Hello build bot (Jenkins), Subrata Banik, Kangheui Won, Nick Vaccaro, Julius Werner, Angel Pons, Arthur Heymans, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68641 to look at the new patch set (#3). Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache ...................................................................... arch/x86/postcar_loader: Don't add postcar to stage cache In romstage, CBMEM and TSEG are not yet cached, so reading/writing to the stage cache is slow. This means there isn't really any benefit to adding postcar to the stage cache: - During boot, adding it to the stage cache adds a few ms of boot time, since writing to uncached memory is slow. - During S3 resume, reading from stage cache takes roughly the same time as reading from SPI, so we get little or no savings anyway. E.g. on nivviks, this change saves 6 ms of boot time and 2 ms of S3 resume time. Adding postcar to stage cache: Boot: rmodule_stage_load() - 4 ms stage_cache_add() - 6 ms S3 resume: stage_cache_load_stage() - 6 ms Not adding postcar to stage cache: Boot: rmodule_stage_load() - 4 ms S3 resume: rmodule_stage_load() - 4 ms Savings: Boot time - 6 ms S3 resume time - 2 ms ------------------------------------ Savings on other devices: nivviks anahera kindred treeya rmodule_stage_load() 4.0 1.4 0.8 2.8 stage_cache_add() 6.0 2.8 1.5 2.0 stage_cache_load_stage() 6.0 2.8 1.5 2.0 Boot time savings 6.0 2.8 1.5 2.0 S3 resume time savings 2.0 1.4 0.7 -0.8 Note AMD platforms from zork onwards don't use postcar due to PSP verstage. BUG=b:247940538 TEST=On nivviks, boot and check S3 resume still works. Add logging to check postcar is added to stage cache when POSTCAR_IN_STAGE_CACHE is selected, and not added otherwise. Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/arch/x86/Kconfig M src/arch/x86/postcar_loader.c 2 files changed, 70 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68641/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1 Gerrit-Change-Number: 68641 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache
by Arthur Heymans (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Subrata Banik, Reka Norman, Nick Vaccaro, Julius Werner, Angel Pons, Karthikeyan Ramasubramanian. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68641 ) Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache ...................................................................... Patch Set 2: Code-Review-2 (1 comment) Patchset: PS2: The reason for using a stage cache in TSEG for the S3 resume path is for security reasons. After SMM is locked down, that memory cannot be modified by the OS. The SPI flash on the other hand can be modified if we are on a RW_A/B path. Also whether reading from cached SPI flash (with prefetch enabled) is faster than reading uncached DRAM is probably platform dependent. Also https://review.coreboot.org/c/coreboot/+/36674/22 does set up caching for the stage cache region (and cbmem). Maybe that will provide you some performance boosts? -- To view, visit https://review.coreboot.org/c/coreboot/+/68641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1 Gerrit-Change-Number: 68641 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Oct 2022 08:22:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
by build bot (Jenkins) (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68665 ) Change subject: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU ...................................................................... Patch Set 1: (3 comments) File src/mainboard/google/brya/variants/kuldax/ramstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160963): https://review.coreboot.org/c/coreboot/+/68665/comment/0ccaf56f_5cf630b3 PS1, Line 69: if (fw_config_probe(FW_CONFIG(BJ_POWER, BJ_POWER_65W))) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160963): https://review.coreboot.org/c/coreboot/+/68665/comment/e6c57685_00767fb7 PS1, Line 70: variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); line length of 98 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160963): https://review.coreboot.org/c/coreboot/+/68665/comment/c4eae086_fcb2387d PS1, Line 72: variant_update_psys_power_limits(limits, revise_sys_limits, total_entries, &psys_config); line length of 105 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/68665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 Gerrit-Change-Number: 68665 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 08:06:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
by David Wu (Code Review) 21 Oct '22

21 Oct '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68665 ) Change subject: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU ...................................................................... mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W based on fw_config. BUG=b:253542746 TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 --- M src/mainboard/google/brya/variants/kuldax/overridetree.cb M src/mainboard/google/brya/variants/kuldax/ramstage.c 2 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/68665/1 diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index 8471272..f5bd1e0 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -3,6 +3,12 @@ option AUDIO_UNKNOWN 0 option NAU88L25B_I2S 1 end + field BJ_POWER 3 4 + option BJ_POWER_150W 0 + option BJ_POWER_230W 1 + option BJ_POWER_65W 2 + option BJ_POWER_135W 3 + end end chip soc/intel/alderlake diff --git a/src/mainboard/google/brya/variants/kuldax/ramstage.c b/src/mainboard/google/brya/variants/kuldax/ramstage.c index 14a365a..cb0873c 100644 --- a/src/mainboard/google/brya/variants/kuldax/ramstage.c +++ b/src/mainboard/google/brya/variants/kuldax/ramstage.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> +#include <fw_config.h> #include <intelblocks/power_limit.h> const struct cpu_power_limits limits[] = { @@ -26,6 +27,15 @@ { PCI_DID_INTEL_ADL_P_ID_3, 28, 150 }, }; +const struct system_power_limits revise_sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 150 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 150 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 150 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 150 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 150 }, +}; + /* * Psys_pmax considerations. * @@ -55,6 +65,12 @@ void variant_devtree_update(void) { size_t total_entries = ARRAY_SIZE(limits); - variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + + if (fw_config_probe(FW_CONFIG(BJ_POWER, BJ_POWER_65W))) { + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + } else { + variant_update_psys_power_limits(limits, revise_sys_limits, total_entries, &psys_config); + } + variant_update_power_limits(limits, total_entries); } -- To view, visit https://review.coreboot.org/c/coreboot/+/68665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 Gerrit-Change-Number: 68665 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Update RAM ID table
by Frank Wu (Code Review) 21 Oct '22

21 Oct '22

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68664 ) Change subject: mb/google/skyrim/var/frostflow: Update RAM ID table ...................................................................... mb/google/skyrim/var/frostflow: Update RAM ID table Add new ram_id:0100 for memory Samsung K3LKBKB0BM-MGCP. Add new ram_id:0101 for memory Samsung K3LKCKC0BM-MGCP. The RAM ID table has been assigned as: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNCP3MLYR-N6E 1 (0001) MT62F2G32D8DR-031 WT:B 2 (0010) H9JCNNNFA5MLYR-N6E 3 (0011) K3LKBKB0BM-MGCP 4 (0100) K3LKCKC0BM-MGCP 5 (0101) BUG=b:254758998 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I8ff879ff7185f5a0ca1b9632820aba3b0f5d02c6 --- M src/mainboard/google/skyrim/variants/frostflow/memory/Makefile.inc M src/mainboard/google/skyrim/variants/frostflow/memory/dram_id.generated.txt M src/mainboard/google/skyrim/variants/frostflow/memory/mem_parts_used.txt 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/68664/1 diff --git a/src/mainboard/google/skyrim/variants/frostflow/memory/Makefile.inc b/src/mainboard/google/skyrim/variants/frostflow/memory/Makefile.inc index f6c1d1a..23382dc 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/memory/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/frostflow/memory/Makefile.inc @@ -8,3 +8,5 @@ SPD_SOURCES += spd/lp5/set-1/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E SPD_SOURCES += spd/lp5/set-1/spd-4.hex # ID = 2(0b0010) Parts = MT62F2G32D8DR-031 WT:B SPD_SOURCES += spd/lp5/set-1/spd-9.hex # ID = 3(0b0011) Parts = H9JCNNNFA5MLYR-N6E +SPD_SOURCES += spd/lp5/set-1/spd-3.hex # ID = 4(0b0100) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-1/spd-6.hex # ID = 5(0b0101) Parts = K3LKCKC0BM-MGCP diff --git a/src/mainboard/google/skyrim/variants/frostflow/memory/dram_id.generated.txt b/src/mainboard/google/skyrim/variants/frostflow/memory/dram_id.generated.txt index 1384f14..8a415d4 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/memory/dram_id.generated.txt +++ b/src/mainboard/google/skyrim/variants/frostflow/memory/dram_id.generated.txt @@ -10,3 +10,5 @@ H9JCNNNCP3MLYR-N6E 1 (0001) MT62F2G32D8DR-031 WT:B 2 (0010) H9JCNNNFA5MLYR-N6E 3 (0011) +K3LKBKB0BM-MGCP 4 (0100) +K3LKCKC0BM-MGCP 5 (0101) diff --git a/src/mainboard/google/skyrim/variants/frostflow/memory/mem_parts_used.txt b/src/mainboard/google/skyrim/variants/frostflow/memory/mem_parts_used.txt index c1e7c07..a0e7ae0 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/memory/mem_parts_used.txt +++ b/src/mainboard/google/skyrim/variants/frostflow/memory/mem_parts_used.txt @@ -4,3 +4,5 @@ H9JCNNNCP3MLYR-N6E, MT62F2G32D8DR-031 WT:B, H9JCNNNFA5MLYR-N6E, +K3LKBKB0BM-MGCP, +K3LKCKC0BM-MGCP, -- To view, visit https://review.coreboot.org/c/coreboot/+/68664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ff879ff7185f5a0ca1b9632820aba3b0f5d02c6 Gerrit-Change-Number: 68664 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache
by Kangheui Won (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Subrata Banik, Reka Norman, Nick Vaccaro, Julius Werner, Angel Pons, Arthur Heymans, Karthikeyan Ramasubramanian. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68641 ) Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68641/comment/2b273a68_8833360e PS2, Line 40: treeya Can you also test on Zork or MI devices since they have different flow due to psp-verstage? -- To view, visit https://review.coreboot.org/c/coreboot/+/68641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1 Gerrit-Change-Number: 68641 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Oct 2022 07:01:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control
by Kangheui Won (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: V Sowmya, Tim Wawrzynczak. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68252 ) Change subject: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5 Gerrit-Change-Number: 68252 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 06:58:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
by Rex-BC Chen (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68659/comment/2c70b383_a1d6cbd1 PS2, Line 10: winbond > please fill the model name Done https://review.coreboot.org/c/coreboot/+/68659/comment/f58558b1_1ebc81d1 PS2, Line 14: We change the NOR flash clcok parent and adjust the clock from 52M to > remove this paragraph Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 05:49:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
by Rex-BC Chen (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: verify pass by ODM. -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 05:48:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022