coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[S] Change in coreboot[master]: mb/siemens/mc_ehl1: Disable L1 prefetcher
by Werner Zeh (Code Review) 21 Oct '22

21 Oct '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68668 ) Change subject: mb/siemens/mc_ehl1: Disable L1 prefetcher ...................................................................... mb/siemens/mc_ehl1: Disable L1 prefetcher The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/68668/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 44a1c38..1c11008 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -132,6 +132,9 @@ .vcc_low_high_us = 50, }" + # Disable L1 prefetcher + register "L1_prefetcher_disable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/68668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Gerrit-Change-Number: 68668 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
by Werner Zeh (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Lean Sheng Tan. Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68667 ) Change subject: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher ...................................................................... soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher Depending on the real workload that is executed on the system the L1 prefetcher might be too aggressive and will populate the L1 cache ahead with data that is not really needed. This will in the end result in a higher cache miss rate thus slowing down the real application. This patch provides a devicetree option to disable the L1 prefetcher if needed. This can be requested on mainboard level if needed. Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/cpu.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/68667/1 diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index d63844f..94a2cdf 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -454,6 +454,9 @@ * 3600, 3733, 4000, 4200, 4267 and 0 for Auto. */ uint16_t max_dram_speed_mts; + + /* Disable L1 prefetcher */ + bool L1_prefetcher_disable; }; typedef struct soc_intel_elkhartlake_config config_t; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index f4baa65..8ba28c0 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -67,6 +67,14 @@ msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); + + /* In some cases it is beneficial for the performance to disable the + L1 prefetcher as on Elkhart Lake it is set up a bit too aggressive. */ + if (conf->L1_prefetcher_disable) { + msr = rdmsr(MSR_PREFETCH_CTL); + msr.lo |= PREFETCH_L1_DISABLE; + wrmsr(MSR_PREFETCH_CTL, msr); + } } /* All CPUs including BSP will run the following function. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Gerrit-Change-Number: 68667 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants
by Werner Zeh (Code Review) 21 Oct '22

21 Oct '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68666 ) Change subject: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants ...................................................................... mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/68666/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 69277a5..44a1c38 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -126,6 +126,13 @@ register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1" + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index ecf5d55..4109ec9 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -117,6 +117,12 @@ }, }" + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/68666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Gerrit-Change-Number: 68666 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
by Jan Samek (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Werner Zeh, Jan Samek. Jan Samek has uploaded a new patch set (#4) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M ...................................................................... mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases, such as emitting POST codes through a PCIe device. For the initialization to happen properly, certain register writes specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter 3.3.1 have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emitted before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/bootblock.c 1 file changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68223/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Werner Zeh, Jan Samek. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M ...................................................................... Patch Set 3: Code-Review+1 (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68223/comment/37cb13c5_4abf16fb PS3, Line 14: certain cases (like this one - emitting POST codes through a PCIe : device). The text in parentheses feels a bit "loose". How about: > ... in certain cases, such as emitting POST codes through a PCIe device. https://review.coreboot.org/c/coreboot/+/68223/comment/b1a7b25f_e7c4fbfd PS3, Line 17: inicialization nit: ini*t*ialization https://review.coreboot.org/c/coreboot/+/68223/comment/39b5b654_23edee60 PS3, Line 18: IAFW IAFW BIOS spec Looks like the full document title is: ``` Apollo Lake Platform Intel Architecture Firmware Specification (Volume 2 of 2) BIOS Specification ``` Patchset: PS3: Thanks for making this pretty! Will let Werner (or anyone else) give a +2, since we both authored this change. File src/mainboard/siemens/mc_apl1/bootblock.c: https://review.coreboot.org/c/coreboot/+/68223/comment/5ab9836d_fdae6c7c PS3, Line 20: IAFW spec IAFW BIOS spec -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 09:30:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: arch/x86/include/arch: fix assembly clobber for 64bit
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Matei Dibu, Nico Huber, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66345 ) Change subject: arch/x86/include/arch: fix assembly clobber for 64bit ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/66345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Gerrit-Change-Number: 66345 Gerrit-PatchSet: 10 Gerrit-Owner: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 21 Oct 2022 09:26:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: arch/x86/include/arch: fix assembly clobber for 64bit
by Matei Dibu (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Nico Huber, Arthur Heymans. Matei Dibu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66345 ) Change subject: arch/x86/include/arch: fix assembly clobber for 64bit ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/66345/comment/7fe79da8_0ac3be46 PS9, Line 9: the "x86 PIC code ebx" workaround done previously fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/66345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Gerrit-Change-Number: 66345 Gerrit-PatchSet: 10 Gerrit-Owner: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 21 Oct 2022 09:22:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: arch/x86/include/arch: fix assembly clobber for 64bit
by Matei Dibu (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Nico Huber, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Angel Pons, Arthur Heymans, Elyes Haouas, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66345 to look at the new patch set (#10). Change subject: arch/x86/include/arch: fix assembly clobber for 64bit ...................................................................... arch/x86/include/arch: fix assembly clobber for 64bit the "x86 PIC code ebx" workaround done previously by commit 689e31d18b0f ("Make cpuid functions usable when compiled with PIC") does not work for x86_64 (the upper dword of rbx is set to 0) the GCC bug that needed the workaround was fixed in version 5 (see GCC bug 54232) Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Signed-off-by: Matei Dibu <matdibu(a)protonmail.com> --- M src/arch/x86/include/arch/cpuid.h 1 file changed, 46 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/66345/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/66345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Gerrit-Change-Number: 66345 Gerrit-PatchSet: 10 Gerrit-Owner: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: arch/x86/include/arch: fix assembly clobber for 64bit
by Matei Dibu (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Nico Huber, Arthur Heymans. Matei Dibu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66345 ) Change subject: arch/x86/include/arch: fix assembly clobber for 64bit ...................................................................... Patch Set 9: (1 comment) Patchset: PS8: > this needs a rebase it seems yeah, they had been moved to another file -- To view, visit https://review.coreboot.org/c/coreboot/+/66345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Gerrit-Change-Number: 66345 Gerrit-PatchSet: 9 Gerrit-Owner: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 21 Oct 2022 09:15:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: arch/x86/include/arch: fix assembly clobber for 64bit
by build bot (Jenkins) (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Matei Dibu, Nico Huber. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66345 ) Change subject: arch/x86/include/arch: fix assembly clobber for 64bit ...................................................................... Patch Set 9: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160967): https://review.coreboot.org/c/coreboot/+/66345/comment/8b0c1515_6199dfea PS9, Line 9: the "x86 PIC code ebx" workaround done previously Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 689e31d18b0f ("Make cpuid functions usable when compiled with PIC")' -- To view, visit https://review.coreboot.org/c/coreboot/+/66345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Gerrit-Change-Number: 66345 Gerrit-PatchSet: 9 Gerrit-Owner: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 21 Oct 2022 09:14:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2022