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Change subject: mb/prodrive/atlas: add unique DIMM locators in smbios type17
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
File src/mainboard/prodrive/atlas/mainboard.c:
https://review.coreboot.org/c/coreboot/+/68632/comment/e4e5a148_f4576d73
PS1, Line 20: snprintf(dev_loc, sizeof(dev_loc), "DIMM-%d%d%d", mc, ch, mm);
As per the SMBIOS spec, this should be the name of the slot as printed on the mainboard. If memory serves right, the slots are `SO-DIMM A0` and `SO-DIMM B0`. So, this should be:
snprintf(dev_loc, sizeof(dev_loc), "SO-DIMM %c%u", 'A' + mc, mm);
If you don't like the `'A' + mc` part, feel free to change it. But this would be the idea.
https://review.coreboot.org/c/coreboot/+/68632/comment/c5645d3f_a6cb40b1
PS1, Line 24: %d%d%d
nit: use `%u` because unsigned. Also, maaaybe separate the numbers with hyphens or the like for clarity?
https://review.coreboot.org/c/coreboot/+/68632/comment/3a883e76_07ab95e4
PS1, Line 35: MC-%d-CH-%d-DIMM-%d
nit: use `%u` because unsigned.
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Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
Patchset:
PS2:
> I've tested it with coreboot's upstream FSP repository and it seems to work... […]
Oh, sorry for the confusion. We don't have any dependencies on FSP. The problem we have is that on a DDR5 system (mb/prodrive/atlas) with 2 SO-DIMMs, the SMBIOS tables report the same locators for the DIMMs. This is because both SO-DIMMs are on "Channel 0 Slot 0", but one is on Memory Controller 0 and the other one is on Memory Controller 1.
This change shouldn't make any meaningful difference on its own, because the `node_num` field is not consumed (yet).
File src/include/memory_info.h:
https://review.coreboot.org/c/coreboot/+/68525/comment/0fbf54fc_774468e3
PS3, Line 98: uint8_t node_num;
Could you please move this next to the `channel_num` and `dimm_num` fields?
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Change subject: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> from the patch, it looks like Pentium and Celeron match to the ssame PCI_DID_INTEL_ADL_P_ID_10 CPU S […]
Yes, you are right.
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Change subject: soc/amd/acpi: Expand 5 thermal profiles to DPTC
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/alib.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160983):
https://review.coreboot.org/c/coreboot/+/68470/comment/d53a2ab4_2625fe8a
PS7, Line 33:
trailing whitespace
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Tim Van Patten, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/acpi: Expand 5 thermal profiles to DPTC
......................................................................
soc/amd/acpi: Expand 5 thermal profiles to DPTC
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles
User can use these profiles for their specific feature.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
---
M src/soc/amd/common/block/acpi/alib.c
M src/soc/amd/common/block/include/amdblocks/alib.h
2 files changed, 113 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68470/7
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Change subject: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
......................................................................
soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
Expand DPTC for extra 5 DPTC thermal related profiles
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd
---
M src/soc/amd/mendocino/chip.h
1 file changed, 96 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/68469/6
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Change subject: lib/Kconfig: Disable `DECOMPRESS_OFAST` for x86_64
......................................................................
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Change subject: lib/lzma: Build the source for decompression with flag -Ofast
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
Looks like this broke QEMU i440fx x86_64... CB:68648 fixes it.
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Change subject: lib/Kconfig: Disable `DECOMPRESS_OFAST` for x86_64
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