coreboot-gerrit October 2022

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[S] Change in coreboot[master]: lib/Kconfig: Disable `DECOMPRESS_OFAST` for x86_64
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68648 ) Change subject: lib/Kconfig: Disable `DECOMPRESS_OFAST` for x86_64 ...................................................................... lib/Kconfig: Disable `DECOMPRESS_OFAST` for x86_64 Commit d91f3a4eaf7f8399db83a9c2d5cba2452fefaf7a ("lib/lzma: Build the source for decompression with flag -Ofast") enabled optimizations for LZMA at build time, but these seem to break loading compressed stages on at least QEMU i440fx when using 64-bit coreboot. This results in a boot loop when attempting to load ramstage. For the time being, don't enable `DECOMPRESS_OFAST` when `USE_EXP_X86_64_SUPPORT` is enabled. TEST=Ensure that `configs/config.emulation_qemu_x86_i440fx_x86_64` is is able to reach the payload instead of boot-looping when trying to load ramstage. Payload-specific functionality not tested. Change-Id: I4e1475b71754cdda309b6c4ed72086c084dbcb1f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/Kconfig 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/68648/1 diff --git a/src/lib/Kconfig b/src/lib/Kconfig index ae96fc6..6bed740 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -118,6 +118,6 @@ config DECOMPRESS_OFAST bool depends on COMPILER_GCC - default y + default y if !USE_EXP_X86_64_SUPPORT help Compile the decompressing function in -Ofast instead of standard -Os -- To view, visit https://review.coreboot.org/c/coreboot/+/68648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1475b71754cdda309b6c4ed72086c084dbcb1f Gerrit-Change-Number: 68648 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya: Enable SaGv for brask variants
by Derek Huang (Code Review) 21 Oct '22

21 Oct '22

Derek Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68646 ) Change subject: mb/google/brya: Enable SaGv for brask variants ...................................................................... mb/google/brya: Enable SaGv for brask variants SaGv is enabled for all brya variants, so it should be harmless to enable it for brask variants and can save some power. BUG=254374912 TEST=Build and boot to Chrome OS Signed-off-by: Derek Huang <derekhuang(a)google.com> Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed --- M src/mainboard/google/brya/variants/brask/overridetree.cb M src/mainboard/google/brya/variants/gaelin/overridetree.cb M src/mainboard/google/brya/variants/kuldax/overridetree.cb M src/mainboard/google/brya/variants/moli/overridetree.cb 4 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/68646/1 diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 88c73ad..6c66d79 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -6,6 +6,8 @@ end chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + device domain 0 on device ref dtt on chip drivers/intel/dptf diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index 4f2c04a..caa874b 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -1,4 +1,5 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" device domain 0 on end diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index 8471272..fdf37d5 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -6,6 +6,8 @@ end chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 2d35e14..5612b6e 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -14,6 +14,7 @@ end end chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" # Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2 register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, -- To view, visit https://review.coreboot.org/c/coreboot/+/68646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed Gerrit-Change-Number: 68646 Gerrit-PatchSet: 1 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
by EricKY Cheng (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Ian Feng, Matt DeVillier, Chris Wang, Tim Van Patten, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Tim Van Patten, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68469 to look at the new patch set (#5). Change subject: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles ...................................................................... soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles Expand DPTC for extra 5 DPTC thermal related profiles BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd --- M src/soc/amd/mendocino/chip.h 1 file changed, 96 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/68469/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Gerrit-Change-Number: 68469 Gerrit-PatchSet: 5 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
by Derek Huang (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: David Wu, YH Lin, Ren Kuo, Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, Peter Ou. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68665 ) Change subject: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: from the patch, it looks like Pentium and Celeron match to the ssame PCI_DID_INTEL_ADL_P_ID_10 CPU SKU ID, so you use fw_config to apply different psys value, am I correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/68665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 Gerrit-Change-Number: 68665 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 10:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl1: Disable L1 prefetcher
by Werner Zeh (Code Review) 21 Oct '22

21 Oct '22

Werner Zeh has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/68668 ) Change subject: mb/siemens/mc_ehl1: Disable L1 prefetcher ...................................................................... mb/siemens/mc_ehl1: Disable L1 prefetcher The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/68668/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Gerrit-Change-Number: 68668 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants
by Werner Zeh (Code Review) 21 Oct '22

21 Oct '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68666 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants ...................................................................... mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/68666/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Gerrit-Change-Number: 68666 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
by Werner Zeh (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Angel Pons, Jan Samek. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 10:03:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Werner Zeh, Jan Samek. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 10:00:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock
by Werner Zeh (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Lean Sheng Tan. Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68669 ) Change subject: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock ...................................................................... mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock After some measurements it turned out that Elkhart Lake uses a higher CSR clock internally from which the MDIO clock is derived. In order to stay compliant with the specification, the MDIO clock needs to be lower than 2.5 MHz. Therefore, the divider needs to be 102 and not 62. This patch changes the define to match the new divider value and uses this new define at the appropriate place. Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz. Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h M src/soc/intel/elkhartlake/tsn_gbe.c 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/68669/1 diff --git a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h index b1d04cc..cd9f12e 100644 --- a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h +++ b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h @@ -15,7 +15,7 @@ #define TSN_MAC_PHYAD(pa) (pa << 21) /* Physical Layer Address */ #define TSN_MAC_REGAD(rda) (rda << 16) /* Register/Device Address */ #define TSN_MAC_CLK_TRAIL_4 (4 << 12) /* 4 Trailing Clocks */ -#define TSN_MAC_CSR_CLK_DIV_62 (1 << 8) /* 0001: CSR=100-150 MHz; CSR/62 */ +#define TSN_MAC_CSR_CLK_DIV_102 (1 << 10) /* 0100: CSR=150-250 MHz; CSR/102 */ #define TSN_MAC_OP_CMD_WRITE (1 << 2) /* GMII Operation Command Write */ #define TSN_MAC_OP_CMD_READ (3 << 2) /* GMII Operation Command Read */ #define TSN_MAC_GMII_BUSY (1 << 0) /* GMII Busy bit */ diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index 3e08897..2a1468c 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -52,7 +52,7 @@ clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 + | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 | TSN_MAC_OP_CMD_READ | TSN_MAC_GMII_BUSY); /* Wait for MDIO frame transfer to complete before reading MDIO DATA register */ @@ -75,7 +75,7 @@ write16(base + TSN_MAC_MDIO_DATA, data); clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 + | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 | TSN_MAC_OP_CMD_WRITE | TSN_MAC_GMII_BUSY); /* Wait for MDIO frame transfer to complete before do next */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
by Jan Samek (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Angel Pons, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68223/comment/e20e6925_06415dc4 PS3, Line 14: certain cases (like this one - emitting POST codes through a PCIe : device). > The text in parentheses feels a bit "loose". How about: […] Done https://review.coreboot.org/c/coreboot/+/68223/comment/689bdd6a_6cc97b31 PS3, Line 17: inicialization > nit: ini*t*ialization oh, a mix of 3 languages.. pretty https://review.coreboot.org/c/coreboot/+/68223/comment/d7d6b762_4ccfd85e PS3, Line 18: IAFW > IAFW BIOS spec […] Done File src/mainboard/siemens/mc_apl1/bootblock.c: https://review.coreboot.org/c/coreboot/+/68223/comment/5bd1fc05_93b8f0f3 PS3, Line 20: IAFW spec > IAFW BIOS spec Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 09:58:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2022