coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: scripts/update_submodules: Fix "bad revision" error
by Elyes Haouas (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68650 to look at the new patch set (#4). Change subject: scripts/update_submodules: Fix "bad revision" error ...................................................................... scripts/update_submodules: Fix "bad revision" error Fix "bad revision" error when we run "update_submodules" with no option. This adds "origin/trunk" branch name for "util/goswid". Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/scripts/update_submodules 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/68650/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Gerrit-Change-Number: 68650 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86/include/arch: fix assembly clobber for 64bit
by Elyes Haouas (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Matei Dibu, Nico Huber, Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66345 ) Change subject: arch/x86/include/arch: fix assembly clobber for 64bit ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Gerrit-Change-Number: 66345 Gerrit-PatchSet: 10 Gerrit-Owner: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 21 Oct 2022 12:03:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: scripts/update_submodules: Fix "bad revision" error
by Elyes Haouas (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68650 to look at the new patch set (#3). Change subject: scripts/update_submodules: Fix "bad revision" error ...................................................................... scripts/update_submodules: Fix "bad revision" error Fix "bad revision" error when we run "update_submodules" with no option. This adds "origin/trunk" branch name for "util/goswid". Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/scripts/update_submodules 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/68650/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Gerrit-Change-Number: 68650 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: scripts/update_submodules: Fix "bad revision" error
by Elyes Haouas (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68650 to look at the new patch set (#2). Change subject: scripts/update_submodules: Fix "bad revision" error ...................................................................... scripts/update_submodules: Fix "bad revision" error Fix "bad revision" error when we run "update_submodules" whit no option. This adds "origin/trunk" branch name for util/goswid". Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/scripts/update_submodules 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/68650/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Gerrit-Change-Number: 68650 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jonathan Zhang, Arthur Heymans, Andrey Petrov, Tarun Tuli, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Christian Walter, Kapil Porwal, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, David Milosevic, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68525 ) Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill ...................................................................... Patch Set 3: (1 comment) File src/include/memory_info.h: https://review.coreboot.org/c/coreboot/+/68525/comment/9aefecc8_e6423233 PS3, Line 98: uint8_t node_num; > I was thinking about this, but I came to the conclusion that it might be better to not mess with the […] It's just a data struct, so there's no problem if the offsets change. The only reason it might be packed is to minimize space usage. -- To view, visit https://review.coreboot.org/c/coreboot/+/68525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Gerrit-Change-Number: 68525 Gerrit-PatchSet: 3 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 11:53:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: scripts/update_submodules: Fix "bad revision" error
by Elyes Haouas (Code Review) 21 Oct '22

21 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68650 ) Change subject: scripts/update_submodules: Fix "bad revision" error ...................................................................... scripts/update_submodules: Fix "bad revision" error This adds "origin/trunk" branch name. Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/scripts/update_submodules 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/68650/1 diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules index 6b8eb09..4ca2925 100755 --- a/util/scripts/update_submodules +++ b/util/scripts/update_submodules @@ -110,8 +110,10 @@ if git branch -a | grep -q "origin/main"; then branch_name="origin/main" - else + elif git branch -a | grep -q "origin/master"; then branch_name="origin/master" + elif git branch -a | grep -q "origin/trunk"; then + branch_name="origin/trunk" fi updated_commit_id="$(git log --pretty='%h' -n 1 "${branch_name}" -- )" -- To view, visit https://review.coreboot.org/c/coreboot/+/68650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Gerrit-Change-Number: 68650 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
by David Milosevic (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Tarun Tuli, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Christian Walter, Kapil Porwal, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, Tim Chu. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68525 ) Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill ...................................................................... Patch Set 3: (1 comment) File src/include/memory_info.h: https://review.coreboot.org/c/coreboot/+/68525/comment/17d00f72_9dc562b3 PS3, Line 98: uint8_t node_num; > Could you please move this next to the `channel_num` and `dimm_num` fields? I was thinking about this, but I came to the conclusion that it might be better to not mess with the offsets within the structure, since I don't know exactly how the structure is currently being used elsewhere. But if you still don't have any concerns, I would move it next to channel_num. -- To view, visit https://review.coreboot.org/c/coreboot/+/68525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Gerrit-Change-Number: 68525 Gerrit-PatchSet: 3 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 11:42:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Yidi Lin, Yu-Ping Wu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz ...................................................................... Patch Set 3: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68659/comment/15252201_fab44c42 PS3, Line 10: Mhz nit: capitalize the 'h'? `MHz` https://review.coreboot.org/c/coreboot/+/68659/comment/4fe7750e_a6b45e02 PS3, Line 11: 52Mhz to 39 Mhz nit: Same as above. Also, let's be consistent with (not) having space before `MHz` 😄 https://review.coreboot.org/c/coreboot/+/68659/comment/1bcf0a23_d0bba436 PS3, Line 17: BRAHCH typo: BRA*N*CH -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 11:40:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Expand DPTC_INPUT input value
by build bot (Jenkins) (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Expand DPTC_INPUT input value ...................................................................... Patch Set 1: (4 comments) File src/soc/amd/mendocino/root_complex.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160985): https://review.coreboot.org/c/coreboot/+/68649/comment/6efc8771_5ba4843d PS1, Line 32: _sttSkinTempLimit, stt_AlphaApu,_sttErrCoeff, _sttErrRateCoeff) \ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160985): https://review.coreboot.org/c/coreboot/+/68649/comment/51de99c3_11cd3d5a PS1, Line 241: _sttMinLimit, _sttM1, _sttM2, _sttCApu, \ Avoid unnecessary line continuations Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160985): https://review.coreboot.org/c/coreboot/+/68649/comment/17647f27_0d5a13fd PS1, Line 242: _sttSkinTempLimit, stt_AlphaApu,_sttErrCoeff, _sttErrRateCoeff) \ space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160985): https://review.coreboot.org/c/coreboot/+/68649/comment/55764b8f_82ca785f PS1, Line 274: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Oct 2022 11:37:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Expand DPTC_INPUT input value
by EricKY Cheng (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. EricKY Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Expand DPTC_INPUT input value ...................................................................... soc/amd/mendocino: Expand DPTC_INPUT input value Expand DPTC_INPUT value BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 --- M src/soc/amd/mendocino/root_complex.c 1 file changed, 127 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68649/1 diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6768613..d5a457c 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +a/* SPDX-License-Identifier: GPL-2.0-only */ /* TODO: Check if this is still correct */ @@ -18,15 +18,18 @@ #include <stdint.h> #include "chip.h" -#define DPTC_TOTAL_UPDATE_PARAMS 7 +#define DPTC_TOTAL_UPDATE_PARAMS 15 struct dptc_input { uint16_t size; struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; } __packed; + #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow, \ - _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit) \ + _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ + _sttMinLimit, _sttM1, _sttM2, _sttCApu, \ + _sttSkinTempLimit, stt_AlphaApu,_sttErrCoeff, _sttErrRateCoeff) \ { \ .size = sizeof(struct dptc_input), \ .params = { \ @@ -55,8 +58,36 @@ .value = _vrmMaxCurrentLimit, \ }, \ { \ - .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ - .value = _vrmSocCurrentLimit, \ + .id = ALIB_DPTC_STT_MIN_LIMIT_ID, \ + .value = _sttMinLimit, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M1_ID, \ + .value = _sttM1, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M2_ID, \ + .value = _sttM2, \ + }, \ + { \ + .id = ALIB_DPTC_STT_C_APU_ID, \ + .value = _sttCApu, \ + }, \ + { \ + .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID, \ + .value = _sttSkinTempLimit, \ + }, \ + { \ + .id = ALIB_DPTC_STT_ALPHA_APU_ID, \ + .value = stt_AlphaApu, \ + }, \ + { \ + .id = ALIB_DPTC_STT_ERROR_COEFF_ID, \ + .value = _sttErrCoeff, \ + }, \ + { \ + .id = ALIB_DPTC_STT_ERROR_RATE_COEFF_ID, \ + .value = _sttErrRateCoeff, \ }, \ }, \ } @@ -200,6 +231,15 @@ { const struct soc_amd_mendocino_config *config = config_of_soc(); +uint16_t stt_m1_B; + uint16_t stt_m2_B; + uint16_t stt_c_apu_B; + uint16_t stt_skin_temp_apu_B; + uint16_t stt_alpha_apu_B; + uint16_t stt_error_coeff_B; + uint16_t stt_error_rate_coefficient_B; +_sttMinLimit, _sttM1, _sttM2, _sttCApu, \ + _sttSkinTempLimit, stt_AlphaApu,_sttErrCoeff, _sttErrRateCoeff) \ /* Normal mode DPTC values. */ struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, config->sustained_power_limit_mW, @@ -207,7 +247,16 @@ config->slow_ppt_limit_mW, config->vrm_current_limit_mA, config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA); + config->vrm_soc_current_limit_mA, + config->stt_min_limit, + config->stt_m1, + config->stt_m2, + config->stt_c_apu, + config->stt_skin_temp_apu, + config->stt_alpha_apu, + config->stt_error_coeff, + config->stt_error_rate_coefficient + ); acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); /* Low/No Battery */ @@ -221,6 +270,62 @@ config->vrm_soc_current_limit_throttle_mA); acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, sizeof(no_battery_input)); + + + struct dptc_input thermal_B_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_B, + config->sustained_power_limit_mW_B, + config->fast_ppt_limit_mW_B, + config->slow_ppt_limit_mW_B, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, + sizeof(thermal_B_input)); + + struct dptc_input thermal_C_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_C, + config->sustained_power_limit_mW_C, + config->fast_ppt_limit_mW_C, + config->slow_ppt_limit_mW_C, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, + sizeof(thermal_C_input)); + + struct dptc_input thermal_D_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_D, + config->sustained_power_limit_mW_D, + config->fast_ppt_limit_mW_D, + config->slow_ppt_limit_mW_D, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, + sizeof(thermal_D_input)); + + struct dptc_input thermal_E_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_E, + config->sustained_power_limit_mW_E, + config->fast_ppt_limit_mW_E, + config->slow_ppt_limit_mW_E, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, + sizeof(thermal_E_input)); + + struct dptc_input thermal_F_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_F, + config->sustained_power_limit_mW_F, + config->fast_ppt_limit_mW_F, + config->slow_ppt_limit_mW_F, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, + sizeof(thermal_F_input)); } static void root_complex_fill_ssdt(const struct device *device) -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022