[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache

[Arthur Heymans (Code Review)]

Attention is currently required from: Subrata Banik, Reka Norman, Nick Vaccaro, Julius Werner, Angel Pons, Karthikeyan Ramasubramanian.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68641 )

Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache
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Patch Set 2: Code-Review-2

(1 comment)

Patchset:

PS2: 
The reason for using a stage cache in TSEG for the S3 resume path is for security reasons. After SMM is locked down, that memory cannot be modified by the OS. The SPI flash on the other hand can be modified if we are on a RW_A/B path.

Also whether reading from cached SPI flash (with prefetch enabled) is faster than reading uncached DRAM is probably platform dependent.

Also https://review.coreboot.org/c/coreboot/+/36674/22 does set up caching for the stage cache region (and cbmem). Maybe that will provide you some performance boosts?