coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
by Rex-BC Chen (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, Bayi Cheng, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68659 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz ...................................................................... soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz According to the datasheet, the maximum frequency supported by {winbond SPI model} is 50Mhz. To meet this restriction, we lower the NOR clock from 52Mhz to 39 Mhz which is the closest frequency of the next clock level on MT8186. We change the NOR flash clcok parent and adjust the clock from 52M to 39M which is the next lower level of clock for MT8186 NOR. BUG=b:253167106 TEST=emerge-corsola coreboot. TEST=Boot time didn't increase significantly. BRAHCH=corsola Signed-off-by: Dandan He <dandan.he(a)mediatek.corp-partner.google.com> Signed-off-by: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd --- M src/soc/mediatek/mt8186/pll.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/68659/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
by Rex-BC Chen (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: wait for report from ODM. -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 03:16:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
by build bot (Jenkins) (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160955): https://review.coreboot.org/c/coreboot/+/68659/comment/2c61000c_24b7b1c8 PS1, Line 14: We change the NOR flash clcok parent and adjust the clock from 52M to 39M Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 03:16:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp: Get rid of last "sabrina" reference
by Martin L Roth (Code Review) 21 Oct '22

21 Oct '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68645 ) Change subject: vc/amd/fsp: Get rid of last "sabrina" reference ...................................................................... vc/amd/fsp: Get rid of last "sabrina" reference We still had a lingering reference to the old sabrina codename in the vendorcode directory. Searching through the code now, the only places the sabrina codename is seen is in the release notes, as is proper. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 --- M src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h 1 file changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/68645/1 diff --git a/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h b/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h index 76c85bc..35948ff 100644 --- a/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h +++ b/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SABRINA_FSP_CCX_CPPC_DATA_H -#define SABRINA_FSP_CCX_CPPC_DATA_H +#ifndef FSP_MDN_CCX_CPPC_DATA_H +#define FSP_MDN_CCX_CPPC_DATA_H #include <types.h> @@ -14,4 +14,4 @@ uint32_t ccx_cppc_nom_speed; } __packed; -#endif /* SABRINA_FSP_CCX_CPPC_DATA_H */ +#endif /* FSP_MDN_CCX_CPPC_DATA_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 Gerrit-Change-Number: 68645 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
by Rex-BC Chen (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Bayi Cheng. Hello Bayi Cheng, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68659 to review the following change. Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz ...................................................................... soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz According to the datasheet, the maximum frequency supported by {winbond SPI model} is 50Mhz. To meet this restriction, we lower the NOR clock from 52Mhz to 39 Mhz which is the closest frequency of the next clock level on MT8186. We change the NOR flash clcok parent and adjust the clock from 52M to 39M which is the next lower level of clock for MT8186 NOR. BUG=b:253167106 TEST=emerge-corsola coreboot. TEST=Boot time didn't increase significantly. BRAHCH=corsola Signed-off-by: Dandan He <dandan.he(a)mediatek.corp-partner.google.com> Signed-off-by: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd --- M src/soc/mediatek/mt8186/pll.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/68659/1 diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index a6165ef..0a036e2 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -253,7 +253,7 @@ { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d3_d2 */ { .id = TOP_SPMI_MST_SEL, .sel = 2 }, /* 2: ulposc1_d4 */ /* CLK_CFG_13 */ - { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d3_d8 */ + { .id = TOP_SPINOR_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */ { .id = TOP_NNA_SEL, .sel = 14 }, /* 14: nnapll_ck */ { .id = TOP_NNA1_SEL, .sel = 14 }, /* 14: nnapll_ck */ { .id = TOP_NNA2_SEL, .sel = 15 }, /* 15: nna2pll_ck */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
by EricKY Cheng (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Ian Feng, Matt DeVillier, Chris Wang, Tim Van Patten, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68469 ) Change subject: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/mendocino/chip.h: https://review.coreboot.org/c/coreboot/+/68469/comment/4430d80a_67fbbf3f PS4, Line 77: uint32_t sustained_power_limit_mW_B; : uint32_t fast_ppt_limit_mW_B; : uint32_t slow_ppt_limit_mW_B; : uint32_t slow_ppt_time_constant_s_B; : uint32_t thermctl_limit_degreeC_B; > From the tables in b/248086651, how are you deciding which values need entries here? […] 1. OK, I will remove the same for everything items. 2. The items list here are for the thermal table expansion design in the future. 2.1. Based on previous co-operation experience with thermal team on lock-down the tables in b/248086651, these parameters list here are probability changed in further tuning. 2.2. There are some table parameters that I don't list here as you expect because based on previous co-operation experience with thermal team on lock-down the tables in b/248086651, thermal team did't request to change. -- To view, visit https://review.coreboot.org/c/coreboot/+/68469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Gerrit-Change-Number: 68469 Gerrit-PatchSet: 4 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Oct 2022 03:15:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/i945.h: Drop useless guard
by 9elements QA (Code Review) 21 Oct '22

21 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68215 ) Change subject: nb/intel/i945/i945.h: Drop useless guard ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129506 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/129505 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/129504 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/129503 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/129502 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129501 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/129500 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/129499 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/129498 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/129497 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129496 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129495 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129494 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129493 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129492 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129491 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 Gerrit-Change-Number: 68215 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 21 Oct 2022 03:12:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/cbmem: Update formatting for cbmem -l command
by Martin L Roth (Code Review) 21 Oct '22

21 Oct '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68644 ) Change subject: util/cbmem: Update formatting for cbmem -l command ...................................................................... util/cbmem: Update formatting for cbmem -l command Some of the cbmem area names have gotten longer, and were making the output of cbmem -l look bad, so expand the name area to 20 characters. Instead of printing a blank area if the name isn't recognized, call it unknown. Change the method of printing the title to match the way the actual text of the table is printed. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0 --- M util/cbmem/cbmem.c 1 file changed, 24 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/68644/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index c537a7a..2c9255d 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1185,11 +1185,10 @@ printf("%2d. ", n); if (name == NULL) - printf("\t\t%08x", id); - else - printf("%s\t%08x", name, id); + name = "UNKNOWN"; + printf("%-20s %08x", name, id); printf(" %08" PRIx64 " ", base); - printf(" %08" PRIx64 "\n", size); + printf(" %08" PRIx64 "\n", size); } static void dump_cbmem_toc(void) @@ -1204,7 +1203,8 @@ return; printf("CBMEM table of contents:\n"); - printf(" NAME ID START LENGTH\n"); + printf(" %-20s %-8s %-8s %-8s\n", "NAME", "ID", "START", + "LENGTH"); i = 0; offset = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/68644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0 Gerrit-Change-Number: 68644 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control
by Baieswara Reddy Sagili (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: V Sowmya, Kangheui Won, Tim Wawrzynczak. Baieswara Reddy Sagili has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68252 ) Change subject: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5 Gerrit-Change-Number: 68252 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 02:56:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Update devicetree setting
by Frank Wu (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jason Nien, Kangheui Won, Isaac Lee, Jon Murphy, Martin Roth, Karthik Ramasubramanian. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68482 ) Change subject: mb/google/skyrim/var/frostflow: Update devicetree setting ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: Hi Matt, Could you check Karthik's comment? Thank you. File src/mainboard/google/skyrim/variants/frostflow/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68482/comment/3c1a1293_11a4ff7c PS3, Line 111: GPIO_24 > I think the GPIO config in variants/baseboard/gpio. […] Based on the comment, I created the another CL to update the IRQ setting in baseboard/gpio.c. Thank you. Here is the CL: https://review.coreboot.org/c/coreboot/+/68638 -- To view, visit https://review.coreboot.org/c/coreboot/+/68482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia03962b0e01394ddcd4971cbe0172ef5bd913e15 Gerrit-Change-Number: 68482 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 02:55:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2022