coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd/mendocino: Add STB Spill-to-DRAM enum
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68686 ) Change subject: soc/amd/mendocino: Add STB Spill-to-DRAM enum ...................................................................... soc/amd/mendocino: Add STB Spill-to-DRAM enum This is the enum value to initialize the Smart Trace Buffer's Spill-to-DRAM feature. More information on how this is used is available in the STB Linux kernel driver. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 --- M src/soc/amd/mendocino/include/soc/smu.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/68686/1 diff --git a/src/soc/amd/mendocino/include/soc/smu.h b/src/soc/amd/mendocino/include/soc/smu.h index c2c629e..b811aca 100644 --- a/src/soc/amd/mendocino/include/soc/smu.h +++ b/src/soc/amd/mendocino/include/soc/smu.h @@ -12,6 +12,7 @@ enum smu_message_id { SMC_MSG_S3ENTRY = 0x0b, + SMC_MSG_SET_S2D_ADDR = 0x53, }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/68686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 Gerrit-Change-Number: 68686 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel/i945/raminit: Use 'bool' for do_reset
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68217 ) Change subject: nb/intel/i945/raminit: Use 'bool' for do_reset ...................................................................... nb/intel/i945/raminit: Use 'bool' for do_reset Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/68217 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 18 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 47a37ce..2613b81 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -216,7 +216,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) { u8 reg8; - u8 do_reset = 0; + bool do_reset = false; reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); @@ -225,7 +225,7 @@ printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); - do_reset = 1; + do_reset = true; } @@ -233,7 +233,7 @@ printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1 << 7); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); - do_reset = 1; + do_reset = true; } /* Set SLP_S3# Assertion Stretch Enable */ @@ -258,12 +258,12 @@ if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && !(mchbar_read8(SLFRCS) & (1 << 0))) { - do_reset = 1; + do_reset = true; } if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) && !(mchbar_read8(SLFRCS) & (1 << 1))) { - do_reset = 1; + do_reset = true; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea Gerrit-Change-Number: 68217 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68216 ) Change subject: nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7 ...................................................................... nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68216 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h 2 files changed, 19 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 7b8c84d..47a37ce 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1604,7 +1604,8 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) { u8 reg8; - u8 freq, second_vco, voltage; + u8 freq, voltage; + bool second_vco = false; #define CRCLK_166MHz 0x00 #define CRCLK_200MHz 0x01 @@ -1680,10 +1681,8 @@ else sysinfo->mvco4x = 0; - second_vco = 0; - if (voltage == VOLTAGE_1_50) { - second_vco = 1; + second_vco = true; } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { u16 mem = sysinfo->memory_frequency; u16 fsb = sysinfo->fsb_frequency; @@ -1691,17 +1690,14 @@ if ((fsb == 667 && mem == 533) || (fsb == 533 && mem == 533) || (fsb == 533 && mem == 400)) { - second_vco = 1; + second_vco = true; } if (fsb == 667 && mem == 533) sysinfo->mvco4x = 1; } - if (second_vco) - sysinfo->clkcfg_bit7 = 1; - else - sysinfo->clkcfg_bit7 = 0; + sysinfo->clkcfg_bit7 = second_vco; /* Graphics Core Render Clock */ pci_update_config16(IGD_DEV, GCFC, ~((7 << 0) | (1 << 13)), freq); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index efaedf4..22c4faf 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -30,7 +30,7 @@ bool interleaved; u8 mvco4x; /* 0 (8x) or 1 (4x) */ - u8 clkcfg_bit7; + bool clkcfg_bit7; u8 boot_path; #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 Gerrit-Change-Number: 68216 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: smbios.h: Add High Bandwidth Memory Generation 3
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65356 ) Change subject: smbios.h: Add High Bandwidth Memory Generation 3 ...................................................................... smbios.h: Add High Bandwidth Memory Generation 3 Add HBM3 according to SMBIOS 3.6.0: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau… Change-Id: Id8473e8c4b5006b53b5ff9de7825d15595f2a616 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65356 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/smbios.h 1 file changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/include/smbios.h b/src/include/smbios.h index 65522f0..3611eb6 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -210,6 +210,7 @@ MEMORY_TYPE_HBM2 = 0x21, MEMORY_TYPE_DDR5 = 0x22, MEMORY_TYPE_LPDDR5 = 0x23, + MEMORY_TYPE_HBM3 = 0x24, } smbios_memory_type; typedef enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/65356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8473e8c4b5006b53b5ff9de7825d15595f2a616 Gerrit-Change-Number: 65356 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i945/raminit: Use 'size_t' for banksize[]
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68213 ) Change subject: nb/intel/i945/raminit: Use 'size_t' for banksize[] ...................................................................... nb/intel/i945/raminit: Use 'size_t' for banksize[] Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68213 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h 2 files changed, 18 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c9b0837..7b8c84d 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -426,11 +426,12 @@ die("DDR-II rank size smaller than 128MB is not supported.\n"); sysinfo->banksize[i * 2] = dimm_info.ranksize_mb / 32; - printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); + printk(BIOS_DEBUG, "DIMM %d side 0 = %zu MB\n", i, + sysinfo->banksize[i * 2] * 32); if (dimm_info.ranks == 2) { sysinfo->banksize[(i * 2) + 1] = dimm_info.ranksize_mb / 32; - printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", + printk(BIOS_DEBUG, "DIMM %d side 1 = %zu MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32); } @@ -1142,7 +1143,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom, pci_mmio_size; + size_t cum0, cum1, tolud, tom, pci_mmio_size; const struct device *dev; const struct northbridge_intel_i945_config *cfg = NULL; diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index d69110e..efaedf4 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -49,7 +49,7 @@ #define SYSINFO_DIMM_NOT_POPULATED 0x04 u8 banks[2 * DIMM_SOCKETS]; - u8 banksize[2 * 2 * DIMM_SOCKETS]; + size_t banksize[2 * 2 * DIMM_SOCKETS]; const u8 *spd_addresses; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/68213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa Gerrit-Change-Number: 68213 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68553 ) Change subject: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130077 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130076 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130075 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130074 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130073 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130072 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130071 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130070 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130069 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130068 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130067 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130066 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130065 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130064 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130063 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130062 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Gerrit-Change-Number: 68553 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 04:29:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/lenovo/*/mainboard.c: Clean up includes
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68017 ) Change subject: mb/lenovo/*/mainboard.c: Clean up includes ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130060 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130059 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130058 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130057 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130056 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130055 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130054 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130053 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130052 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130051 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130050 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130049 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130048 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130047 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130046 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130045 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408 Gerrit-Change-Number: 68017 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 04:15:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update opensbi submodule to upstream master
by build bot (Jenkins) (Code Review) 22 Oct '22

22 Oct '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68655 ) Change subject: Update opensbi submodule to upstream master ...................................................................... Patch Set 2: (3 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161028): https://review.coreboot.org/c/coreboot/+/68655/comment/186a8d94_f8451bd7 PS2, Line 12: to commit id b6e520b: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161028): https://review.coreboot.org/c/coreboot/+/68655/comment/75327b7b_ed630d1b PS2, Line 16: b6e520b platform: generic: allwinner: add support for c9xx pmu Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161028): https://review.coreboot.org/c/coreboot/+/68655/comment/581a669d_1a33ea9e PS2, Line 17: 2f63f24 platform: generic: add extensions_init handler and platform-override Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e90f9f89effa4d1e641723859885d5874f4c7c0 Gerrit-Change-Number: 68655 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 04:12:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update intel-sec-tools submodule to upstream master
by build bot (Jenkins) (Code Review) 22 Oct '22

22 Oct '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68654 ) Change subject: Update intel-sec-tools submodule to upstream master ...................................................................... Patch Set 2: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161027): https://review.coreboot.org/c/coreboot/+/68654/comment/8daa8f0e_51f59b4d PS2, Line 9: Updating from commit id 0031ac7: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161027): https://review.coreboot.org/c/coreboot/+/68654/comment/a26e0849_16c440e8 PS2, Line 12: to commit id a4552d6: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0769b3b90c58cece514d9e0ec4c08653ec57ddaf Gerrit-Change-Number: 68654 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 04:12:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Update fsp submodule to upstream master
by build bot (Jenkins) (Code Review) 22 Oct '22

22 Oct '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68653 ) Change subject: Update fsp submodule to upstream master ...................................................................... Patch Set 2: (3 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161026): https://review.coreboot.org/c/coreboot/+/68653/comment/ecb4764a_96839383 PS2, Line 20: e14d687 Delete ElkhartLake_FSP_Integration_Guide.pdf 'Readme' may be misspelled - perhaps 'Readme'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161026): https://review.coreboot.org/c/coreboot/+/68653/comment/8f974ee5_481326ea PS2, Line 21: 7c1f6a2 Readme.md 'README' may be misspelled - perhaps 'README'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161026): https://review.coreboot.org/c/coreboot/+/68653/comment/fe7ee09e_d27f571f PS2, Line 44: 13a144f Added IoT ADL-PS PV (3354_00) FSP 'README' may be misspelled - perhaps 'README'? -- To view, visit https://review.coreboot.org/c/coreboot/+/68653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d8984ed79e6b1ce4978a83e180b569493f47a18 Gerrit-Change-Number: 68653 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 04:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022