coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[XL] Change in coreboot[master]: util/docker/coreboot.org-status: Rewrite parser
by Maxim Polyakov (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Georgi, Martin L Roth, ron minnich. Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59958 ) Change subject: util/docker/coreboot.org-status: Rewrite parser ...................................................................... Patch Set 15: Code-Review+1 (5 comments) Patchset: PS15: Are you planning to create unit tests? File util/docker/coreboot.org-status/board-status.html/logs.go: https://review.coreboot.org/c/coreboot/+/59958/comment/55b69eb2_148f40f2 PS15, Line 26: _ logging of this error is not required? https://github.com/golang/go/blob/master/src/io/fs/walk.go#L117 https://review.coreboot.org/c/coreboot/+/59958/comment/e096841d_a6b3aafa PS15, Line 61: item What happens if the string doesn't contain the ":" character? https://go.dev/play/p/6I70DRcEp_m check len(item) needed? https://review.coreboot.org/c/coreboot/+/59958/comment/4f622eba_b87d83d0 PS15, Line 93: [3] check len(pieces) needed? File util/docker/coreboot.org-status/board-status.html/status-to-html.go: https://review.coreboot.org/c/coreboot/+/59958/comment/4703b88f_3922e7d1 PS15, Line 71: dirs Why are you using the channel here? Why not a slice? In my opinion, it would be better to abandon multithreading to make the algorithm easier. How critical is performance? -- To view, visit https://review.coreboot.org/c/coreboot/+/59958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2 Gerrit-Change-Number: 59958 Gerrit-PatchSet: 15 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 11:12:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michael Niewöhner (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Felix Singer, Michał Kopeć, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 16: (4 comments) Patchset: PS16: a File src/mainboard/clevo/tgl-u/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/62498/comment/d444c89e_8ce69e5a PS3, Line 6: GPD9 GPD3? GPD9 is SLP_WLAN# File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c: https://review.coreboot.org/c/coreboot/+/62498/comment/9ec5a169_2eccf51b PS6, Line 129: //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ : //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ : > We thought some options were added to FSP so that it leaves GPIOs alone. […] There is a option with three possible degrees of "leaving gpios alone". TGL currently only sets the first one. ``` Help "Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable;1: Level 1 - skips GpioSetNativePadByFunction;Level 2 - skips GpioSetNativePadByFunction and GpioSetPadMode" ``` ``` src/soc/intel/tigerlake/romstage/fsp_params.c: m_cfg->GpioOverride = 0x1; ``` File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c: https://review.coreboot.org/c/coreboot/+/62498/comment/7eeed456_b93acbe6 PS16, Line 13: params->CpuPcieRpLtrEnable[0] = 1; : params->CpuPcieRpSlotImplemented[0] = 1; > No devicetree settings for these? not yet, unfortunately; there is a change from me for that somewhere -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 09:28:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/mediatek/mt8188: Add ddp driver to support eDP output
by Yidi Lin (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68487 ) Change subject: soc/mediatek/mt8188: Add ddp driver to support eDP output ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388 Gerrit-Change-Number: 68487 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 07:17:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68216 ) Change subject: nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7 ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130145 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130144 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130143 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130142 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130141 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130140 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130139 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130138 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130137 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130136 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130135 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130134 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130133 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130132 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130131 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130130 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 Gerrit-Change-Number: 68216 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 06:37:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update intel-sec-tools submodule to upstream master
by Elyes Haouas (Code Review) 22 Oct '22

22 Oct '22

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/68654 ) Change subject: Update intel-sec-tools submodule to upstream master ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/68654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0769b3b90c58cece514d9e0ec4c08653ec57ddaf Gerrit-Change-Number: 68654 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: console: Add an SoC-specific post-code call
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Julius Werner, Angel Pons, Martin Roth. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68545 ) Change subject: console: Add an SoC-specific post-code call ...................................................................... Patch Set 4: (1 comment) File src/console/post.c: https://review.coreboot.org/c/coreboot/+/68545/comment/3a362c5e_3e1b7220 PS1, Line 22: uint32_t > > If you want, I can update it to 8-bit for now, and expand it to 32-bits later as part of the overa […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Gerrit-Change-Number: 68545 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 05:32:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Add code for printing STB to boot log
by build bot (Jenkins) (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68544 ) Change subject: soc/amd/mendocino: Add code for printing STB to boot log ...................................................................... Patch Set 3: Verified+1 (1 comment) File src/soc/amd/mendocino/include/soc/stb.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161031): https://review.coreboot.org/c/coreboot/+/68544/comment/0120f40b_6c4c0a4a PS3, Line 6: #define STB_CFG_SMN_ADDR 0x3E00000 please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/68544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66 Gerrit-Change-Number: 68544 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 22 Oct 2022 05:31:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common: Add coreboot post codes to STB
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68546 to look at the new patch set (#3). Change subject: soc/amd/common: Add coreboot post codes to STB ...................................................................... soc/amd/common: Add coreboot post codes to STB Adding coreboot's postcodes to the smart trace buffer lets us see the entire boot flow in one place. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa --- M src/soc/amd/common/block/include/amdblocks/stb.h M src/soc/amd/common/block/stb/Kconfig M src/soc/amd/common/block/stb/stb.c 3 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/68546/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa Gerrit-Change-Number: 68546 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Add code for printing STB to boot log
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68544 to look at the new patch set (#3). Change subject: soc/amd/mendocino: Add code for printing STB to boot log ...................................................................... soc/amd/mendocino: Add code for printing STB to boot log This adds the mendocino specific code for printing the STB data to the boot log. It still needs to be enabled in the mainboard to be used. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66 --- M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/early_fch.c A src/soc/amd/mendocino/include/soc/stb.h M src/soc/amd/mendocino/romstage.c 4 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/68544/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66 Gerrit-Change-Number: 68544 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: console: Add an SoC-specific post-code call
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Martin L Roth, Angel Pons, Martin Roth. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68545 to look at the new patch set (#3). Change subject: console: Add an SoC-specific post-code call ...................................................................... console: Add an SoC-specific post-code call Add a post-code call that SoCs can hook to output or save in any way that is specific to that SoC. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 --- M src/console/post.c M src/include/console/console.h 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/68545/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Gerrit-Change-Number: 68545 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022