coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd/*/i2c.h: Make definition more accurate
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68682 ) Change subject: soc/amd/*/i2c.h: Make definition more accurate ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130043 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130042 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130041 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130040 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130039 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130038 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130037 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130036 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130035 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130034 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130033 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130032 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130031 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130030 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130029 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130028 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Gerrit-Change-Number: 68682 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 03:41:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp: Get rid of last "sabrina" reference
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68645 ) Change subject: vc/amd/fsp: Get rid of last "sabrina" reference ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130026 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130025 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130024 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130023 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130022 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130021 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130020 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130019 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130018 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130017 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130016 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130015 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130014 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130013 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130012 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130011 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 Gerrit-Change-Number: 68645 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 03:27:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/kahlee: Fix audio ACPI inclusion
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68583 ) Change subject: mb/google/kahlee: Fix audio ACPI inclusion ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130009 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130008 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130007 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130006 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130005 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130004 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130003 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130002 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130001 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130000 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/129999 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/129998 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/129997 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/129996 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/129995 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/129994 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Gerrit-Change-Number: 68583 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 02:52:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/fsp: Get rid of last "sabrina" reference
by Felix Held (Code Review) 22 Oct '22

22 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68645 ) Change subject: vc/amd/fsp: Get rid of last "sabrina" reference ...................................................................... vc/amd/fsp: Get rid of last "sabrina" reference We still had a lingering reference to the old sabrina codename in the vendorcode directory. Searching through the code now, the only places the sabrina codename is seen is in the release notes, as is proper. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h 1 file changed, 21 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h b/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h index 76c85bc..35948ff 100644 --- a/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h +++ b/src/vendorcode/amd/fsp/mendocino/ccx_cppc_data.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SABRINA_FSP_CCX_CPPC_DATA_H -#define SABRINA_FSP_CCX_CPPC_DATA_H +#ifndef FSP_MDN_CCX_CPPC_DATA_H +#define FSP_MDN_CCX_CPPC_DATA_H #include <types.h> @@ -14,4 +14,4 @@ uint32_t ccx_cppc_nom_speed; } __packed; -#endif /* SABRINA_FSP_CCX_CPPC_DATA_H */ +#endif /* FSP_MDN_CCX_CPPC_DATA_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 Gerrit-Change-Number: 68645 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/*/i2c.h: Make definition more accurate
by Felix Held (Code Review) 22 Oct '22

22 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68682 ) Change subject: soc/amd/*/i2c.h: Make definition more accurate ...................................................................... soc/amd/*/i2c.h: Make definition more accurate Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL definitions instead of BIT(x). Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/include/soc/i2c.h M src/soc/amd/mendocino/include/soc/i2c.h M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/i2c.h 4 files changed, 24 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/i2c.h b/src/soc/amd/cezanne/include/soc/i2c.h index c0e3e80..fa7a5e4 100644 --- a/src/soc/amd/cezanne/include/soc/i2c.h +++ b/src/soc/amd/cezanne/include/soc/i2c.h @@ -10,7 +10,8 @@ #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C0_SCL_PIN GPIO_145 diff --git a/src/soc/amd/mendocino/include/soc/i2c.h b/src/soc/amd/mendocino/include/soc/i2c.h index 157ac86..c691267 100644 --- a/src/soc/amd/mendocino/include/soc/i2c.h +++ b/src/soc/amd/mendocino/include/soc/i2c.h @@ -10,7 +10,8 @@ #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C0_SCL_PIN GPIO_145 diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 7056272..6a4d1ff 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -8,7 +8,7 @@ #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19 diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 505802e..0ffff37 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -10,7 +10,8 @@ #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C0_SCL_PIN GPIO_145 #define I2C1_SCL_PIN GPIO_147 -- To view, visit https://review.coreboot.org/c/coreboot/+/68682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Gerrit-Change-Number: 68682 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/*/i2c.h: Make definition more accurate
by Felix Held (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68682 ) Change subject: soc/amd/*/i2c.h: Make definition more accurate ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Gerrit-Change-Number: 68682 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 01:58:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
by Felix Held (Code Review) 22 Oct '22

22 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68553 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY ...................................................................... mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY On nissa, the pre-x86 time is not part of the 1s firmware boot time target. Including the pre-x86 timestamps causes confusion since the boot time appears to be greater than 1s, so disable the Kconfig on nissa. We're not doing any analysis or optimisation of the pre-x86 time on nissa anyway, this work will start from MTL onwards. Also, the Kconfig is already disabled on the brya firmware branch, so this will result in the same behaviour as brya. Before: Total Time: 1,205,840 After: Total Time: 995,300 BUG=b:239769532 TEST=Boot nivviks, check "1st timestamp" is the first timestamp. Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/Kconfig 2 files changed, 35 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved Kangheui Won: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 577c2ca..7b1b783 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -44,6 +44,7 @@ select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 @@ -58,6 +59,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select TPM_GOOGLE_CR50 config BOARD_GOOGLE_BASEBOARD_NISSA @@ -81,6 +83,7 @@ select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SOC_INTEL_RAPTORLAKE select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1474ce8..08a56c4 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -117,7 +117,6 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY if SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Gerrit-Change-Number: 68553 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sam McNally <sammc(a)google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/lenovo/*/mainboard.c: Clean up includes
by Felix Held (Code Review) 22 Oct '22

22 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68017 ) Change subject: mb/lenovo/*/mainboard.c: Clean up includes ...................................................................... mb/lenovo/*/mainboard.c: Clean up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68017 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/lenovo/t410/mainboard.c M src/mainboard/lenovo/t420/mainboard.c M src/mainboard/lenovo/t420s/mainboard.c M src/mainboard/lenovo/t430/mainboard.c M src/mainboard/lenovo/t430s/mainboard.c M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t530/mainboard.c M src/mainboard/lenovo/x131e/mainboard.c M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x220/mainboard.c M src/mainboard/lenovo/x230/mainboard.c 13 files changed, 14 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index 26a0f92..13cafba 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include "dock.h" static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index c8b212c..50c944e 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index c8b212c..50c944e 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index c8b212c..50c944e 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index c8b212c..50c944e 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index d5703f9..39790f2 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> /* mainboard_enable is executed as first thing after enumerate_buses(). */ diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 33c95c2..b33e229 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> // mainboard_enable is executed as first thing after // enumerate_buses(). diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index c8b212c..50c944e 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index c8b212c..50c944e 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 0fc77d3..4b2f253 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> -#include "dock.h" static void fill_ssdt(const struct device *device) { diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 1a306b1..951058b 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <device/device.h> #include <ec/acpi/ec.h> -#include <northbridge/intel/ironlake/ironlake.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "dock.h" #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 33c95c2..b33e229 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> // mainboard_enable is executed as first thing after // enumerate_buses(). diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 33c95c2..b33e229 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> // mainboard_enable is executed as first thing after // enumerate_buses(). -- To view, visit https://review.coreboot.org/c/coreboot/+/68017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408 Gerrit-Change-Number: 68017 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/kahlee: Fix audio ACPI inclusion
by Felix Held (Code Review) 22 Oct '22

22 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68583 ) Change subject: mb/google/kahlee: Fix audio ACPI inclusion ...................................................................... mb/google/kahlee: Fix audio ACPI inclusion Not all kahlee variants use the RT5682 audio codec, so split the baseboard audio ACPI into two parts and only include the asl for the codec(s) actually needed for a given variant. TEST=build/boot aleena, liara variants and verify no ACPI present for RT5682 codec (which is not present on the boards). Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl A src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_da7219.asl A src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_rt5682.asl M src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl 9 files changed, 88 insertions(+), 62 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl index 7aefe2c..c4b5018 100644 --- a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/audio.asl> +#include <baseboard/acpi/audio_da7219.asl> diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl deleted file mode 100644 index bb92243..0000000 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio_map.h> - -/* Grunt specific I2S machine driver */ -Device (I2S0) -{ - Name (_HID, "AMD7219") - Name (_CID, "AMD7219") - - /* Device-Specific Data */ - Name (_DSD, Package () - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () { "bt-pad-enable", 1 }, - } - }) - - Method (_CRS, 0x0, Serialized) { - Name (RBUF, ResourceTemplate () { - // Memory resource is for MISC FCH register set. - // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) - }) - - Return (RBUF) - } -} - -Device (I2S1) -{ - Name (_HID, "AMDI5682") - Name (_CID, "AMDI5682") - - /* Device-Specific Data */ - Name (_DSD, Package () - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () { "bt-pad-enable", 1 }, - } - }) - - Method (_CRS, 0x0, Serialized) { - Name (RBUF, ResourceTemplate () { - // Memory resource is for MISC FCH register set. - // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) - }) - - Return (RBUF) - } -} diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_da7219.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_da7219.asl new file mode 100644 index 0000000..1a08343 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_da7219.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio_map.h> + +/* Grunt specific I2S machine driver */ +Device (I2S0) +{ + Name (_HID, "AMD7219") + Name (_CID, "AMD7219") + + /* Device-Specific Data */ + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "bt-pad-enable", 1 }, + } + }) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + // Memory resource is for MISC FCH register set. + // It is needed for enabling the clock. + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + + Return (RBUF) + } +} diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_rt5682.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_rt5682.asl new file mode 100644 index 0000000..9e3ae05 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio_rt5682.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio_map.h> + +/* Grunt specific I2S machine driver */ +Device (I2S1) +{ + Name (_HID, "AMDI5682") + Name (_CID, "AMDI5682") + + /* Device-Specific Data */ + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "bt-pad-enable", 1 }, + } + }) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + // Memory resource is for MISC FCH register set. + // It is needed for enabling the clock. + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + + Return (RBUF) + } +} diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl index 7aefe2c..86e4053 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl @@ -1,3 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/audio.asl> +#include <baseboard/acpi/audio_da7219.asl> +#include <baseboard/acpi/audio_rt5682.asl> diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl index 7aefe2c..c4b5018 100644 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/audio.asl> +#include <baseboard/acpi/audio_da7219.asl> diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl index 7aefe2c..c4b5018 100644 --- a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/audio.asl> +#include <baseboard/acpi/audio_da7219.asl> diff --git a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl index 7aefe2c..c4b5018 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/audio.asl> +#include <baseboard/acpi/audio_da7219.asl> diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl index 7aefe2c..86e4053 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl @@ -1,3 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/audio.asl> +#include <baseboard/acpi/audio_da7219.asl> +#include <baseboard/acpi/audio_rt5682.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/68583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Gerrit-Change-Number: 68583 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04
by Felix Held (Code Review) 22 Oct '22

22 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68424 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04 ...................................................................... vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04 Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04. Changes include: - FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD BUG=b:254374913 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa. Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176 Signed-off-by: Shaik Shahina <shahina.shaik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424 Reviewed-by: Reka Norman <rekanorman(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h 1 file changed, 78 insertions(+), 52 deletions(-) Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h index 05fffb4..057fce7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h @@ -815,9 +815,11 @@ **/ UINT8 PchFivrDynPm; -/** Offset 0x0415 - Reserved +/** Offset 0x0415 - FIVR VCCST ICCMax Control + Enable/Disable FIVR VCCST ICCMax Control. + $EN_DIS **/ - UINT8 Reserved10; + UINT8 PchFivrVccstIccMaxControl; /** Offset 0x0416 - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA @@ -844,7 +846,7 @@ /** Offset 0x041D - Reserved **/ - UINT8 Reserved11[3]; + UINT8 Reserved10[3]; /** Offset 0x0420 - Extended BIOS Direct Read Decode Range base Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. @@ -858,7 +860,7 @@ /** Offset 0x0428 - Reserved **/ - UINT8 Reserved12[12]; + UINT8 Reserved11[12]; /** Offset 0x0434 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] @@ -869,7 +871,7 @@ /** Offset 0x0435 - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved12; /** Offset 0x0436 - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE @@ -987,7 +989,7 @@ /** Offset 0x0455 - Reserved **/ - UINT8 Reserved14; + UINT8 Reserved13; /** Offset 0x0456 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. @@ -1023,7 +1025,7 @@ /** Offset 0x04AF - Reserved **/ - UINT8 Reserved15; + UINT8 Reserved14; /** Offset 0x04B0 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to @@ -1134,7 +1136,7 @@ /** Offset 0x0521 - Reserved **/ - UINT8 Reserved16[8]; + UINT8 Reserved15[8]; /** Offset 0x0529 - Enable VMD controller Enable/disable to VMD controller.0: Disable; 1: Enable(Default) @@ -1193,7 +1195,7 @@ /** Offset 0x058D - Reserved **/ - UINT8 Reserved17[3]; + UINT8 Reserved16[3]; /** Offset 0x0590 - VMD Variable VMD Variable Pointer. @@ -1217,7 +1219,7 @@ /** Offset 0x05A0 - Reserved **/ - UINT8 Reserved18; + UINT8 Reserved17; /** Offset 0x05A1 - Enable/Disable PMC-PD Solution This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution @@ -1272,7 +1274,7 @@ /** Offset 0x05B1 - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved18; /** Offset 0x05B2 - ITBT DMA LTR TCSS DMA1, DMA2 LTR value @@ -1281,7 +1283,7 @@ /** Offset 0x05B6 - Reserved **/ - UINT8 Reserved20; + UINT8 Reserved19; /** Offset 0x05B7 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -1306,7 +1308,7 @@ /** Offset 0x05C7 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved20; /** Offset 0x05C8 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. @@ -1358,7 +1360,7 @@ /** Offset 0x05F3 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved21; /** Offset 0x05F4 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. @@ -1385,7 +1387,7 @@ /** Offset 0x0612 - Reserved **/ - UINT8 Reserved23[2]; + UINT8 Reserved22[2]; /** Offset 0x0614 - Thermal Design Current time window PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. @@ -1434,7 +1436,7 @@ /** Offset 0x063B - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved23; /** Offset 0x063C - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. @@ -1503,7 +1505,7 @@ /** Offset 0x0687 - Reserved **/ - UINT8 Reserved25; + UINT8 Reserved24; /** Offset 0x0688 - CpuBistData Pointer CPU BIST Data @@ -1540,7 +1542,7 @@ /** Offset 0x0693 - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved25; /** Offset 0x0694 - VR Voltage Limit PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV @@ -1555,7 +1557,7 @@ /** Offset 0x06A0 - Reserved **/ - UINT8 Reserved27[7]; + UINT8 Reserved26[7]; /** Offset 0x06A7 - VccIn Aux Imon slope correction PCODE MMIO Mailbox: VccIn Aux Imon slope correction. 0 - Auto Specified in @@ -1565,7 +1567,7 @@ /** Offset 0x06A8 - Reserved **/ - UINT8 Reserved28[2]; + UINT8 Reserved27[2]; /** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable @@ -1574,7 +1576,7 @@ /** Offset 0x06AB - Reserved **/ - UINT8 Reserved29[13]; + UINT8 Reserved28[13]; /** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1597,7 +1599,7 @@ /** Offset 0x06BC - Reserved **/ - UINT8 Reserved30[2]; + UINT8 Reserved29[2]; /** Offset 0x06BE - Min Voltage for C8 PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = @@ -1631,7 +1633,7 @@ /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x06CA - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. This value @@ -1642,7 +1644,7 @@ /** Offset 0x06CB - Reserved **/ - UINT8 Reserved32[32]; + UINT8 Reserved31[32]; /** Offset 0x06EB - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1836,7 +1838,7 @@ /** Offset 0x0894 - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved32; /** Offset 0x0895 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1846,7 +1848,7 @@ /** Offset 0x0896 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer @@ -1856,7 +1858,7 @@ /** Offset 0x089C - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved34; /** Offset 0x089D - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; @@ -1888,7 +1890,7 @@ /** Offset 0x0929 - Reserved **/ - UINT8 Reserved36[28]; + UINT8 Reserved35[28]; /** Offset 0x0945 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. @@ -1946,7 +1948,7 @@ /** Offset 0x09A1 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset Allows to select the downstream port preset value that will be used during phase @@ -2235,7 +2237,7 @@ /** Offset 0x0A45 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved37; /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2410,7 +2412,7 @@ /** Offset 0x0A6B - Reserved **/ - UINT8 Reserved39; + UINT8 Reserved38; /** Offset 0x0A6C - Thermal Device Temperature Decides the temperature. @@ -2435,7 +2437,7 @@ /** Offset 0x0A89 - Reserved **/ - UINT8 Reserved40[3]; + UINT8 Reserved39[3]; /** Offset 0x0A8C - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2485,7 +2487,7 @@ /** Offset 0x0A9C - Reserved **/ - UINT8 Reserved41[4]; + UINT8 Reserved40[4]; /** Offset 0x0AA0 - BgpdtHash[4] BgpdtHash values @@ -2499,7 +2501,7 @@ /** Offset 0x0AC4 - Reserved **/ - UINT8 Reserved42[4]; + UINT8 Reserved41[4]; /** Offset 0x0AC8 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2532,7 +2534,7 @@ /** Offset 0x0ADB - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42; /** Offset 0x0ADC - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only @@ -2632,7 +2634,7 @@ /** Offset 0x0B00 - Reserved **/ - UINT8 Reserved44[12]; + UINT8 Reserved43[12]; /** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. @@ -2725,7 +2727,7 @@ /** Offset 0x0BD1 - Reserved **/ - UINT8 Reserved45[3]; + UINT8 Reserved44[3]; /** Offset 0x0BD4 - CPU PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -3002,7 +3004,7 @@ /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved46[2]; + UINT8 Reserved45[2]; /** Offset 0x0CA4 - LogoPixelHeight Address Address of LogoPixelHeight @@ -3016,7 +3018,7 @@ /** Offset 0x0CAC - Reserved **/ - UINT8 Reserved47[5]; + UINT8 Reserved46[5]; /** Offset 0x0CB1 - RSR feature Enable or Disable RSR feature; 0: Disable; 1: Enable @@ -3026,7 +3028,7 @@ /** Offset 0x0CB2 - Reserved **/ - UINT8 Reserved48[4]; + UINT8 Reserved47[4]; /** Offset 0x0CB6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; @@ -3419,7 +3421,7 @@ /** Offset 0x0D2D - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved48; /** Offset 0x0D2E - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. @@ -3459,7 +3461,7 @@ /** Offset 0x0D3A - Reserved **/ - UINT8 Reserved50[2]; + UINT8 Reserved49[2]; /** Offset 0x0D3C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -3562,7 +3564,7 @@ /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved51[4]; + UINT8 Reserved50[4]; /** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled @@ -3634,7 +3636,7 @@ /** Offset 0x0D82 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51; /** Offset 0x0D83 - Dual Tau Boost Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; 0: @@ -3645,7 +3647,7 @@ /** Offset 0x0D84 - Reserved **/ - UINT8 Reserved53[32]; + UINT8 Reserved52[32]; /** Offset 0x0DA4 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3694,7 +3696,7 @@ /** Offset 0x0DAB - Reserved **/ - UINT8 Reserved54; + UINT8 Reserved53; /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -3846,7 +3848,7 @@ /** Offset 0x0F96 - Reserved **/ - UINT8 Reserved55[16]; + UINT8 Reserved54[16]; /** Offset 0x0FA6 - FOMS Control Policy Choose the Foms Control Policy, Default = 0 @@ -3868,7 +3870,7 @@ /** Offset 0x0FAF - Reserved **/ - UINT8 Reserved56[33]; + UINT8 Reserved55[33]; /** Offset 0x0FD0 - FspEventHandler Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. @@ -3895,7 +3897,7 @@ /** Offset 0x0FD7 - Reserved **/ - UINT8 Reserved57; + UINT8 Reserved56; /** Offset 0x0FD8 - Emmc Tx CMD Delay control register value Please see Tx CMD Delay Control register definition for help @@ -3929,7 +3931,7 @@ /** Offset 0x0FF0 - Reserved **/ - UINT8 Reserved58[69]; + UINT8 Reserved57[69]; /** Offset 0x1035 - Enable VMD Global Mapping Enable/disable to VMD controller.0: Disable; 1: Enable(Default) @@ -3939,7 +3941,7 @@ /** Offset 0x1036 - Reserved **/ - UINT8 Reserved59[138]; + UINT8 Reserved58[138]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3960,7 +3962,7 @@ /** Offset 0x10C0 **/ - UINT8 UnusedUpdSpace45[6]; + UINT8 UnusedUpdSpace44[6]; /** Offset 0x10C6 **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/68424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176 Gerrit-Change-Number: 68424 Gerrit-PatchSet: 4 Gerrit-Owner: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2022