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[S] Change in coreboot[master]: ifdtool: Use chipset to decide if region exists
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68697 ) Change subject: ifdtool: Use chipset to decide if region exists ...................................................................... ifdtool: Use chipset to decide if region exists Remove hardcoded platform code for denverton and use the chipset to detect if a specific region is supported. Change-Id: I6ac79f66395e378f45eba262df914478ff142b1f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c 1 file changed, 22 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/68697/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index d00e609..1d236b3 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -28,22 +28,6 @@ ((const char *)(ptr) >= (base) && \ (const char *)&(ptr)[1] <= (base) + (limit)) -/** - * PLATFORM_HAS_GBE_REGION - some platforms do not support the PCH GbE LAN region - */ -#define PLATFORM_HAS_GBE_REGION (platform != PLATFORM_DNV) - -/* - * PLATFORM_HAS_EC_REGION - some platforms do not support the EC region - */ -#define PLATFORM_HAS_EC_REGION (ifd_version >= IFD_VERSION_2 && platform != PLATFORM_DNV) - -/* - * PLATFORM_HAS_10GBE_X_REGION - some platforms have 1 or more 10GbE LAN regions - */ -#define PLATFORM_HAS_10GBE_0_REGION (platform == PLATFORM_DNV) -#define PLATFORM_HAS_10GBE_1_REGION (platform == PLATFORM_DNV) - int ifd_version; static int chipset; extern unsigned int max_regions; @@ -606,13 +590,13 @@ } /* EC region access only available on v2+ */ - if (PLATFORM_HAS_EC_REGION) + if (region_supported(chipset, REGION_EC)) printf(" EC Region Write Access: %s\n", (flmstr & (1 << (wr_shift + 8))) ? "enabled" : "disabled"); printf(" Platform Data Region Write Access: %s\n", (flmstr & (1 << (wr_shift + 4))) ? "enabled" : "disabled"); - if (PLATFORM_HAS_GBE_REGION) { + if (region_supported(chipset, REGION_GBE)) { printf(" GbE Region Write Access: %s\n", (flmstr & (1 << (wr_shift + 3))) ? "enabled" : "disabled"); } @@ -622,22 +606,22 @@ (flmstr & (1 << (wr_shift + 1))) ? "enabled" : "disabled"); printf(" Flash Descriptor Write Access: %s\n", (flmstr & (1 << wr_shift)) ? "enabled" : "disabled"); - if (PLATFORM_HAS_10GBE_0_REGION) { + if (region_supported(chipset, REGION_10GB_0)) { printf(" 10GbE_0 Write Access: %s\n", (flmstr & (1 << (wr_shift + 11))) ? "enabled" : "disabled"); } - if (PLATFORM_HAS_10GBE_1_REGION) { + if (region_supported(chipset, REGION_10GB_1)) { printf(" 10GbE_1 Write Access: %s\n", (flmstr & (1 << 4)) ? "enabled" : "disabled"); } - if (PLATFORM_HAS_EC_REGION) + if (region_supported(chipset, REGION_EC)) printf(" EC Region Read Access: %s\n", (flmstr & (1 << (rd_shift + 8))) ? "enabled" : "disabled"); printf(" Platform Data Region Read Access: %s\n", (flmstr & (1 << (rd_shift + 4))) ? "enabled" : "disabled"); - if (PLATFORM_HAS_GBE_REGION) { + if (region_supported(chipset, REGION_GBE)) { printf(" GbE Region Read Access: %s\n", (flmstr & (1 << (rd_shift + 3))) ? "enabled" : "disabled"); } @@ -647,11 +631,11 @@ (flmstr & (1 << (rd_shift + 1))) ? "enabled" : "disabled"); printf(" Flash Descriptor Read Access: %s\n", (flmstr & (1 << rd_shift)) ? "enabled" : "disabled"); - if (PLATFORM_HAS_10GBE_0_REGION) { + if (region_supported(chipset, REGION_10GB_0)) { printf(" 10GbE_0 Read Access: %s\n", (flmstr & (1 << (rd_shift + 11))) ? "enabled" : "disabled"); } - if (PLATFORM_HAS_10GBE_1_REGION) { + if (region_supported(chipset, REGION_10GB_1)) { printf(" 10GbE_1 Read Access: %s\n", (flmstr & (1 << 0)) ? "enabled" : "disabled"); } @@ -669,7 +653,7 @@ decode_flmstr(fmba->flmstr1); printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2); decode_flmstr(fmba->flmstr2); - if (PLATFORM_HAS_GBE_REGION) { + if (region_supported(chipset, REGION_GBE)) { printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); decode_flmstr(fmba->flmstr3); if (ifd_version >= IFD_VERSION_2) { -- To view, visit https://review.coreboot.org/c/coreboot/+/68697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ac79f66395e378f45eba262df914478ff142b1f Gerrit-Change-Number: 68697 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: ifdtool: Hardcode supported regions for every chipset
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68696 ) Change subject: ifdtool: Hardcode supported regions for every chipset ...................................................................... ifdtool: Hardcode supported regions for every chipset Hardcode the supported regions for every chipset. This allows to decide if a region is reserved and it allows to get the maximum number of regions per chipset. Update max_regions using the introduced array to prevent corruption of IFDs that have less than 16 regions. Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h M util/ifdtool/regions.c 3 files changed, 70 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/68696/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 69d738f..d00e609 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -275,15 +275,11 @@ if (is_platform_ifd_2()) { ifd_version = IFD_VERSION_2; chipset = ifd2_platform_to_chipset(platform); - if (chipset == CHIPSET_8_SERIES_WELLSBURG) - max_regions = MAX_REGIONS_WBG; - else - max_regions = MAX_REGIONS; } else { ifd_version = IFD_VERSION_1; chipset = ifd1_guess_chipset(image, size); - max_regions = MAX_REGIONS_OLD; } + max_regions = max_regions_per_chipset(chipset); } static void dump_frba(const frba_t *frba) diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 700609b..53f46dc 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -117,7 +117,6 @@ // regions #define MAX_REGIONS 16 -#define MAX_REGIONS_WBG 6 #define MAX_REGIONS_OLD 5 enum flash_regions { @@ -212,4 +211,5 @@ const char *region_filename(unsigned int region_type); void dump_region(unsigned int num, const frba_t *frba); void dump_region_layout(char *buf, size_t bufsize, unsigned int num, - const frba_t *frba); \ No newline at end of file + const frba_t *frba); +int max_regions_per_chipset(const enum ich_chipset chip); \ No newline at end of file diff --git a/util/ifdtool/regions.c b/util/ifdtool/regions.c index 8a22eb0..09c9dbe 100644 --- a/util/ifdtool/regions.c +++ b/util/ifdtool/regions.c @@ -4,6 +4,7 @@ #include <stdlib.h> #include <stdio.h> #include <string.h> +#include <commonlib/helpers.h> #include "ifdtool.h" extern int ifd_version; @@ -28,6 +29,39 @@ { "PTT", "ptt", "flashregion_15_ptt.bin", "SI_PTT" }, }; +/* Bitmask of supported regions per chipset. + * + * Reserved regions are cleared, supported have set the bit. + * The MSB gives the maximum supported region count. + */ +static const uint32_t region_support_by_chipset[] = { // Document Id + [CHIPSET_ICH_UNKNOWN] = 0x1f, + [CHIPSET_ICH7] = 0x1f, + [CHIPSET_ICH8] = 0x1f, + [CHIPSET_ICH9] = 0x1f, + [CHIPSET_ICH10] = 0x1f, + [CHIPSET_PCH_UNKNOWN] = 0x1f, + [CHIPSET_5_SERIES_IBEX_PEAK] = 0x1f, // 403598 + [CHIPSET_6_SERIES_COUGAR_POINT] = 0x1f, + [CHIPSET_7_SERIES_PANTHER_POINT] = 0x1f, // 475653 + [CHIPSET_8_SERIES_LYNX_POINT] = 0x1f, // 489495 + [CHIPSET_BAYTRAIL] = 0x1f, + [CHIPSET_8_SERIES_LYNX_POINT_LP] = 0x1f, + [CHIPSET_8_SERIES_WELLSBURG] = 0x3f, // 516552 + [CHIPSET_9_SERIES_WILDCAT_POINT] = 0x1f, + [CHIPSET_9_SERIES_WILDCAT_POINT_LP] = 0x1f, + [CHIPSET_N_J_SERIES_APOLLO_LAKE] = 0x37, // 559702 + [CHIPSET_N_J_SERIES_GEMINI_LAKE] = 0x11f, // 571036 + [CHIPSET_N_SERIES_JASPER_LAKE] = 0x3f, + [CHIPSET_x6000_SERIES_ELKHART_LAKE] = 0x3f, + [CHIPSET_100_200_SERIES_SUNRISE_POINT] = 0x11f, // 550696 + [CHIPSET_300_SERIES_CANNON_POINT] = 0x3f, + [CHIPSET_400_SERIES_ICE_POINT] = 0x3f, + [CHIPSET_500_600_SERIES_TIGER_ALDER_POINT] = 0x11f, + [CHIPSET_C620_SERIES_LEWISBURG] = 0x9f7f, // 559021 + [CHIPSET_DENVERTON] = 0x1c17, // 559462 +}; + region_t get_region(const frba_t *frba, unsigned int region_type) { int base_mask; @@ -139,4 +173,20 @@ region_t region = get_region(frba, num); snprintf(buf, bufsize, "%08x:%08x %s\n", region.base, region.limit, region_name_short(num)); +} + +int max_regions_per_chipset(const enum ich_chipset chip) +{ + int num = MAX_REGIONS; + if (chip >= ARRAY_SIZE(region_support_by_chipset)) { + fprintf(stderr, "Unknown chipset: %d\n", chip); + return num; + } + + do { + if (region_support_by_chipset[chip] & (1 << num)) + break; + } while (num--); + + return num + 1; } \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/68696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Gerrit-Change-Number: 68696 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: ifdtool: Move regions to seperate file
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68695 ) Change subject: ifdtool: Move regions to seperate file ...................................................................... ifdtool: Move regions to seperate file Change-Id: I6a1ba1799c69881b1f48d903b8f86e7cd93815c2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/Makefile.inc M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h A util/ifdtool/regions.c 4 files changed, 169 insertions(+), 137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/68695/1 diff --git a/util/ifdtool/Makefile.inc b/util/ifdtool/Makefile.inc index eb3a700..9bc8cc2 100644 --- a/util/ifdtool/Makefile.inc +++ b/util/ifdtool/Makefile.inc @@ -1,6 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause -ifdtoolobj = ifdtool.o fmap.o kv_pair.o valstr.o +ifdtoolobj = ifdtool.o regions.o fmap.o kv_pair.o valstr.o IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 3d57e02..69d738f 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -44,31 +44,12 @@ #define PLATFORM_HAS_10GBE_0_REGION (platform == PLATFORM_DNV) #define PLATFORM_HAS_10GBE_1_REGION (platform == PLATFORM_DNV) -static int ifd_version; +int ifd_version; static int chipset; -static unsigned int max_regions = 0; +extern unsigned int max_regions; static int selected_chip = 0; static int platform = -1; -static const struct region_name region_names[MAX_REGIONS] = { - { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, - { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, - { "Intel ME", "me", "flashregion_2_intel_me.bin", "SI_ME" }, - { "GbE", "gbe", "flashregion_3_gbe.bin", "SI_GBE" }, - { "Platform Data", "pd", "flashregion_4_platform_data.bin", "SI_PDR" }, - { "Device Exp1", "devexp", "flashregion_5_device_exp.bin", "SI_DEVICEEXT" }, - { "Secondary BIOS", "bios2", "flashregion_6_bios2.bin", "SI_BIOS2" }, - { "Reserved", "res7", "flashregion_7_reserved.bin", NULL }, - { "EC", "ec", "flashregion_8_ec.bin", "SI_EC" }, - { "Device Exp2", "devexp2", "flashregion_9_device_exp.bin", "SI_DEVICEEXT2" }, - { "IE", "ie", "flashregion_10_ie.bin", "SI_IE" }, - { "10GbE_0", "10gbe_0", "flashregion_11_10gbe0.bin", "SI_10GBE0" }, - { "10GbE_1", "10gbe_1", "flashregion_12_10gbe1.bin", "SI_10GBE1" }, - { "Reserved", "res13", "flashregion_13_reserved.bin", NULL }, - { "Reserved", "res14", "flashregion_14_reserved.bin", NULL }, - { "PTT", "ptt", "flashregion_15_ptt.bin", "SI_PTT" }, -}; - /* port from flashrom */ static const char *const ich_chipset_names[] = { "Unknown ICH", @@ -305,119 +286,6 @@ } } -static region_t get_region(const frba_t *frba, unsigned int region_type) -{ - int base_mask; - int limit_mask; - uint32_t flreg; - region_t region; - - if (ifd_version >= IFD_VERSION_2) - base_mask = 0x7fff; - else - base_mask = 0xfff; - - limit_mask = base_mask << 16; - - if (region_type >= max_regions) { - fprintf(stderr, "Invalid region type %d.\n", region_type); - exit (EXIT_FAILURE); - } - - flreg = frba->flreg[region_type]; - region.base = (flreg & base_mask) << 12; - region.limit = ((flreg & limit_mask) >> 4) | 0xfff; - region.size = region.limit - region.base + 1; - - if (region.size < 0) - region.size = 0; - - return region; -} - -static void set_region(frba_t *frba, unsigned int region_type, - const region_t *region) -{ - if (region_type >= max_regions) { - fprintf(stderr, "Invalid region type %u.\n", region_type); - exit (EXIT_FAILURE); - } - - frba->flreg[region_type] = - (((region->limit >> 12) & 0x7fff) << 16) | - ((region->base >> 12) & 0x7fff); -} - -static const char *region_name(unsigned int region_type) -{ - if (region_type >= max_regions) { - fprintf(stderr, "Invalid region type.\n"); - exit (EXIT_FAILURE); - } - - return region_names[region_type].pretty; -} - -static const char *region_name_fmap(unsigned int region_type) -{ - if (region_type >= max_regions) { - fprintf(stderr, "Invalid region type.\n"); - exit (EXIT_FAILURE); - } - - return region_names[region_type].fmapname; -} - -static const char *region_name_short(unsigned int region_type) -{ - if (region_type >= max_regions) { - fprintf(stderr, "Invalid region type.\n"); - exit (EXIT_FAILURE); - } - - return region_names[region_type].terse; -} - -static int region_num(const char *name) -{ - unsigned int i; - - for (i = 0; i < max_regions; i++) { - if (strcasecmp(name, region_names[i].pretty) == 0) - return i; - if (strcasecmp(name, region_names[i].terse) == 0) - return i; - } - - return -1; -} - -static const char *region_filename(unsigned int region_type) -{ - if (region_type >= max_regions) { - fprintf(stderr, "Invalid region type %d.\n", region_type); - exit (EXIT_FAILURE); - } - - return region_names[region_type].filename; -} - -static void dump_region(unsigned int num, const frba_t *frba) -{ - region_t region = get_region(frba, num); - printf(" Flash Region %d (%s): %08x - %08x %s\n", - num, region_name(num), region.base, region.limit, - region.size < 1 ? "(unused)" : ""); -} - -static void dump_region_layout(char *buf, size_t bufsize, unsigned int num, - const frba_t *frba) -{ - region_t region = get_region(frba, num); - snprintf(buf, bufsize, "%08x:%08x %s\n", - region.base, region.limit, region_name_short(num)); -} - static void dump_frba(const frba_t *frba) { unsigned int i; @@ -1052,8 +920,8 @@ if ((uint)region.base != area->offset || (uint)region.size != area->size) { printf("Region mismatch between %s and %s\n", - region_names[i].terse, area->name); - printf(" Descriptor region %s:\n", region_names[i].terse); + region_name_short(i), area->name); + printf(" Descriptor region %s:\n", region_name_short(i)); printf(" offset: 0x%08x\n", region.base); printf(" length: 0x%08x\n", region.size); printf(" FMAP area %s:\n", area->name); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 0a3444f..700609b 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -201,3 +201,15 @@ const char *filename; const char *fmapname; }; + +region_t get_region(const frba_t *frba, unsigned int region_type); +void set_region(frba_t *frba, unsigned int region_type, + const region_t *region); +const char *region_name(unsigned int region_type); +const char *region_name_short(unsigned int region_type); +const char *region_name_fmap(unsigned int region_type); +int region_num(const char *name); +const char *region_filename(unsigned int region_type); +void dump_region(unsigned int num, const frba_t *frba); +void dump_region_layout(char *buf, size_t bufsize, unsigned int num, + const frba_t *frba); \ No newline at end of file diff --git a/util/ifdtool/regions.c b/util/ifdtool/regions.c new file mode 100644 index 0000000..8a22eb0 --- /dev/null +++ b/util/ifdtool/regions.c @@ -0,0 +1,142 @@ +/* ifdtool - dump Intel Firmware Descriptor information */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include "ifdtool.h" + +extern int ifd_version; +unsigned int max_regions = 0; + +static const struct region_name region_names[MAX_REGIONS] = { + { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, + { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, + { "Intel ME", "me", "flashregion_2_intel_me.bin", "SI_ME" }, + { "GbE", "gbe", "flashregion_3_gbe.bin", "SI_GBE" }, + { "Platform Data", "pd", "flashregion_4_platform_data.bin", "SI_PDR" }, + { "Device Exp1", "devexp", "flashregion_5_device_exp.bin", "SI_DEVICEEXT" }, + { "Secondary BIOS", "bios2", "flashregion_6_bios2.bin", "SI_BIOS2" }, + { "Reserved", "res7", "flashregion_7_reserved.bin", NULL }, + { "EC", "ec", "flashregion_8_ec.bin", "SI_EC" }, + { "Device Exp2", "devexp2", "flashregion_9_device_exp.bin", "SI_DEVICEEXT2" }, + { "IE", "ie", "flashregion_10_ie.bin", "SI_IE" }, + { "10GbE_0", "10gbe_0", "flashregion_11_10gbe0.bin", "SI_10GBE0" }, + { "10GbE_1", "10gbe_1", "flashregion_12_10gbe1.bin", "SI_10GBE1" }, + { "Reserved", "res13", "flashregion_13_reserved.bin", NULL }, + { "Reserved", "res14", "flashregion_14_reserved.bin", NULL }, + { "PTT", "ptt", "flashregion_15_ptt.bin", "SI_PTT" }, +}; + +region_t get_region(const frba_t *frba, unsigned int region_type) +{ + int base_mask; + int limit_mask; + uint32_t flreg; + region_t region; + + if (ifd_version >= IFD_VERSION_2) + base_mask = 0x7fff; + else + base_mask = 0xfff; + + limit_mask = base_mask << 16; + + if (region_type >= max_regions) { + fprintf(stderr, "Invalid region type %d.\n", region_type); + exit (EXIT_FAILURE); + } + + flreg = frba->flreg[region_type]; + region.base = (flreg & base_mask) << 12; + region.limit = ((flreg & limit_mask) >> 4) | 0xfff; + region.size = region.limit - region.base + 1; + + if (region.size < 0) + region.size = 0; + + return region; +} + +void set_region(frba_t *frba, unsigned int region_type, + const region_t *region) +{ + if (region_type >= max_regions) { + fprintf(stderr, "Invalid region type %u.\n", region_type); + exit (EXIT_FAILURE); + } + + frba->flreg[region_type] = + (((region->limit >> 12) & 0x7fff) << 16) | + ((region->base >> 12) & 0x7fff); +} + +const char *region_name(unsigned int region_type) +{ + if (region_type >= max_regions) { + fprintf(stderr, "Invalid region type.\n"); + exit (EXIT_FAILURE); + } + + return region_names[region_type].pretty; +} + +const char *region_name_short(unsigned int region_type) +{ + if (region_type >= max_regions) { + fprintf(stderr, "Invalid region type.\n"); + exit (EXIT_FAILURE); + } + + return region_names[region_type].terse; +} + +const char *region_name_fmap(unsigned int region_type) +{ + if (region_type >= max_regions) { + fprintf(stderr, "Invalid region type.\n"); + exit (EXIT_FAILURE); + } + + return region_names[region_type].fmapname; +} + +int region_num(const char *name) +{ + unsigned int i; + + for (i = 0; i < max_regions; i++) { + if (strcasecmp(name, region_names[i].pretty) == 0) + return i; + if (strcasecmp(name, region_names[i].terse) == 0) + return i; + } + + return -1; +} + +const char *region_filename(unsigned int region_type) +{ + if (region_type >= max_regions) { + fprintf(stderr, "Invalid region type %d.\n", region_type); + exit (EXIT_FAILURE); + } + + return region_names[region_type].filename; +} + +void dump_region(unsigned int num, const frba_t *frba) +{ + region_t region = get_region(frba, num); + printf(" Flash Region %d (%s): %08x - %08x %s\n", + num, region_name(num), region.base, region.limit, + region.size < 1 ? "(unused)" : ""); +} + +void dump_region_layout(char *buf, size_t bufsize, unsigned int num, + const frba_t *frba) +{ + region_t region = get_region(frba, num); + snprintf(buf, bufsize, "%08x:%08x %s\n", + region.base, region.limit, region_name_short(num)); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/68695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a1ba1799c69881b1f48d903b8f86e7cd93815c2 Gerrit-Change-Number: 68695 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ifdtool: Introduce region_name_fmap
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68694 ) Change subject: ifdtool: Introduce region_name_fmap ...................................................................... ifdtool: Introduce region_name_fmap Instead of directly accessing the region_name array use a helper function. Change-Id: Ifc810da1628cebd2728d0185502c462ff9428597 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c 1 file changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/68694/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 9f771cf..3d57e02 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -358,6 +358,16 @@ return region_names[region_type].pretty; } +static const char *region_name_fmap(unsigned int region_type) +{ + if (region_type >= max_regions) { + fprintf(stderr, "Invalid region type.\n"); + exit (EXIT_FAILURE); + } + + return region_names[region_type].fmapname; +} + static const char *region_name_short(unsigned int region_type) { if (region_type >= max_regions) { @@ -1025,7 +1035,7 @@ fmap = (struct fmap *)(image + fmap_loc); for (i = 0; i < max_regions; i++) { - if (region_names[i].fmapname == NULL) + if (region_name_fmap(i) == NULL) continue; region_t region = get_region(frba, i); @@ -1034,7 +1044,7 @@ continue; const struct fmap_area *area = - fmap_find_area(fmap, region_names[i].fmapname); + fmap_find_area(fmap, region_name_fmap(i)); if (!area) continue; -- To view, visit https://review.coreboot.org/c/coreboot/+/68694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc810da1628cebd2728d0185502c462ff9428597 Gerrit-Change-Number: 68694 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ifdtool: Add missing chipset_name
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68693 ) Change subject: ifdtool: Add missing chipset_name ...................................................................... ifdtool: Add missing chipset_name Add denverton soc chipset name. Change-Id: I0fd8494123490d6ccc21af2ed30c30d50ddb4e8e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/68693/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 624ea72..9f771cf 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -95,6 +95,7 @@ "400 series Ice Point", "500 series Tiger Point/ 600 series Alder Point", "C620 series Lewisburg", + "Denverton: C39xx", NULL }; -- To view, visit https://review.coreboot.org/c/coreboot/+/68693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd8494123490d6ccc21af2ed30c30d50ddb4e8e Gerrit-Change-Number: 68693 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ifdtool: Drop chipset without IFD
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68692 ) Change subject: ifdtool: Drop chipset without IFD ...................................................................... ifdtool: Drop chipset without IFD Those chipsets do not have an IFD and where not used within the code. Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/68692/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 043e6ee..624ea72 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -72,12 +72,6 @@ /* port from flashrom */ static const char *const ich_chipset_names[] = { "Unknown ICH", - "ICH", - "ICH2345", - "ICH6", - "SCH U", - "Atom E6xx", - "Atom S1220 S1240 S1260", "ICH7", "ICH8", "ICH9", diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index dbd67f7..0a3444f 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -13,12 +13,6 @@ /* port from flashrom */ enum ich_chipset { CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH, - CHIPSET_ICH2345, - CHIPSET_ICH6, - CHIPSET_POULSBO, /* SCH U* */ - CHIPSET_TUNNEL_CREEK, /* Atom E6xx */ - CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */ CHIPSET_ICH7, CHIPSET_ICH8, CHIPSET_ICH9, -- To view, visit https://review.coreboot.org/c/coreboot/+/68692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Gerrit-Change-Number: 68692 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ifdtool: Cleanup IFDv1 detection
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68680 to look at the new patch set (#2). Change subject: ifdtool: Cleanup IFDv1 detection ...................................................................... ifdtool: Cleanup IFDv1 detection Change https://review.coreboot.org/c/coreboot/+/54305 "util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset" made tje '-p' argument mandatory for IFDv2 platforms. Drop the IFDv2 platform CHIPSET_C620_SERIES_LEWISBURG from IFDv1 detection. Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c 1 file changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/68680/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10 Gerrit-Change-Number: 68680 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/ifdtool: Add Wellsburg support
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer, Angel Pons. Hello build bot (Jenkins), Stefan Reinauer, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68657 to look at the new patch set (#3). Change subject: util/ifdtool: Add Wellsburg support ...................................................................... util/ifdtool: Add Wellsburg support Wellsburg is IFDv2 compatible and supports up to 6 regions. Also add support using the -p argument to specify Wellsburg platform. Make sure to not use 16 regions as default as this corrupts the image when using the layout modification feature. Tested on Intel Grangeville. Documents used: Intel Document Id: 516552 Intel Document Id: 565117 Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Co-developed-by: Julian Elischer <jrelis(a)google.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/68657/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Gerrit-Change-Number: 68657 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: intelp2m/parset: Add unit test
by build bot (Jenkins) (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Maxim Polyakov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67701 ) Change subject: intelp2m/parset: Add unit test ...................................................................... Patch Set 2: Verified-1 (18 comments) File util/intelp2m/parser/test/inteltool_test.log: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/c0cc546d_827d9d17 PS2, Line 18: 0x0400: 0x0000001884000502 GPP_A0 RCIN# trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/29ef473b_dcbe7960 PS2, Line 19: 0x0408: 0x0000301984000402 GPP_A1 LAD0 trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/84571846_9f48389c PS2, Line 20: 0x0428: 0x0000001d84000600 GPP_A5 LFRAME# trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/1cf43d06_f15a6ee3 PS2, Line 22: 0x04b8: 0x0000002f84000102 GPP_A23 GPIO trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/a394bf0d_649ac01f PS2, Line 24: 0x0438: 0xffffffffffffffff GPP_C1 RESERVED trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/538f9e2b_6a759a15 PS2, Line 25: 0x04c0: 0x0000003084000100 GPP_B0 GPIO trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/d3a286b0_0633f203 PS2, Line 26: 0x0578: 0x0000104784000a01 GPP_B23 PCHHOT# trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/c031edb3_458d0131 PS2, Line 32: 0x0400: 0x0000004844000502 GPP_C0 SMBCLK trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/15841dcf_d1710041 PS2, Line 33: 0x0428: 0x0000004d84000100 GPP_C5 GPIO trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/4a4aadea_8a3152ff PS2, Line 34: 0x0430: 0xffffffffffffffff GPP_C6 RESERVED trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/52a7e3ec_deb35986 PS2, Line 35: 0x0438: 0xffffffffffffffff GPP_C7 RESERVED trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/6ef44995_81dc551a PS2, Line 36: 0x04b0: 0x0000005e84000600 GPP_C22 UART2_RTS# trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/9761a59d_f5a65911 PS2, Line 39: 0x0580: 0x0000301884000502 GPP_E0 SATAXPCIE0 trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/81354006_ebda96b3 PS2, Line 41: 0x0740: 0x0000005084000500 GPP_G19 SMI# trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/f6405c13_b4d34bfc PS2, Line 47: 0x0448: 0x0000002104000600 GPD9 SLP_WLAN# trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/3c334d62_da1c5514 PS2, Line 53: 0x0400: 0x0000006d84000500 GPP_I0 DDPB_HPD0 trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/4af35e5c_aaa3ee9c PS2, Line 54: 0x0408: 0x0000006e84000502 GPP_I1 DDPC_HPD1 trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161040): https://review.coreboot.org/c/coreboot/+/67701/comment/18ceea67_e3aaa425 PS2, Line 55: 0x0410: 0x0000006f84000502 GPP_I2 DDPD_HPD2 trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/67701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461 Gerrit-Change-Number: 67701 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 11:17:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/intelp2m/fields: Add unit tests
by Maxim Polyakov (Code Review) 22 Oct '22

22 Oct '22

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68673 ) Change subject: util/intelp2m/fields: Add unit tests ...................................................................... util/intelp2m/fields: Add unit tests Change-Id: I6330855b1c7463a3093b38c54e6cc06c3409009a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/fields/cb/cb_test.go A util/intelp2m/fields/fsp/fsp_test.go A util/intelp2m/fields/raw/raw_test.go A util/intelp2m/fields/test/suite.go 4 files changed, 204 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/68673/1 diff --git a/util/intelp2m/fields/cb/cb_test.go b/util/intelp2m/fields/cb/cb_test.go new file mode 100644 index 0000000..d90036b --- /dev/null +++ b/util/intelp2m/fields/cb/cb_test.go @@ -0,0 +1,48 @@ +package cb_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/fields/cb" + "review.coreboot.org/coreboot.git/util/intelp2m/fields/test" +) + +// sliding-one + +func TestCorebootFields(t *testing.T) { + referenceSlice := []string{ + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RESET(PLTRST), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | (1 << 29), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | (1 << 28), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_TRIG(OFF), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE), PAD_CFG1_TOL_1V8),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_RX_POL(INVERT), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(IOAPIC), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(SCI), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(SMI), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_IRQ_ROUTE(NMI), PAD_IOSSTATE(HIZCRx1)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_IOSSTATE(Tx1RxDCRx1)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_IOSSTATE(Tx0RxDCRx1)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_IOSSTATE(Tx0RxDCRx0)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), PAD_PULL(INVALID)),", // Error invalid TERM value = 8 + "_PAD_CFG_STRUCT(, PAD_FUNC(NF4), PAD_PULL(DN_20K)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(NF2), PAD_PULL(DN_5K)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(NF1), PAD_PULL(INVALID)),", // Error invalid TERM value = 1 + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE), PAD_IOSTERM(ENPD)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), PAD_IOSTERM(DISPUPD)),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | (1 << 1), 0),", + "_PAD_CFG_STRUCT(, PAD_FUNC(GPIO) | 1, 0),", + } + test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", cb.FieldMacros{}) +} diff --git a/util/intelp2m/fields/fsp/fsp_test.go b/util/intelp2m/fields/fsp/fsp_test.go new file mode 100644 index 0000000..90bbc0e --- /dev/null +++ b/util/intelp2m/fields/fsp/fsp_test.go @@ -0,0 +1,46 @@ +package fsp_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/fields/fsp" + "review.coreboot.org/coreboot.git/util/intelp2m/fields/test" +) + +func TestFSPFields(t *testing.T) { + referenceSlice := []string{ + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioPlatformReset, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioHostDeepReset, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLvlEdgDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntEdge, GpioResetPwrGood, GpioTolerance1v8 | GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntApic | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntSci | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntSmi | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntNmi | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, INVALID, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeNative4, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermWpd20K, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeNative2, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermWpd5K, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeNative1, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, INVALID, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutLow, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + "{ GPIO_SKL_H_, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInOut, GpioOutHigh, GpioIntDis | GpioIntLevel, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock } },", + } + test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", fsp.FieldMacros{}) +} diff --git a/util/intelp2m/fields/raw/raw_test.go b/util/intelp2m/fields/raw/raw_test.go new file mode 100644 index 0000000..8cab698 --- /dev/null +++ b/util/intelp2m/fields/raw/raw_test.go @@ -0,0 +1,46 @@ +package raw_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/fields/raw" + "review.coreboot.org/coreboot.git/util/intelp2m/fields/test" +) + +func TestRAWFields(t *testing.T) { + referenceSlice := []string{ + "_PAD_CFG_STRUCT(, 0x80000000, 0x80000000),", + "_PAD_CFG_STRUCT(, 0x40000000, 0x40000000),", + "_PAD_CFG_STRUCT(, 0x20000000, 0x20000000),", + "_PAD_CFG_STRUCT(, 0x10000000, 0x10000000),", + "_PAD_CFG_STRUCT(, 0x08000000, 0x08000000),", + "_PAD_CFG_STRUCT(, 0x04000000, 0x04000000),", + "_PAD_CFG_STRUCT(, 0x02000000, 0x02000000),", + "_PAD_CFG_STRUCT(, 0x01000000, 0x01000000),", + "_PAD_CFG_STRUCT(, 0x00800000, 0x00800000),", + "_PAD_CFG_STRUCT(, 0x00400000, 0x00400000),", + "_PAD_CFG_STRUCT(, 0x00200000, 0x00200000),", + "_PAD_CFG_STRUCT(, 0x00100000, 0x00100000),", + "_PAD_CFG_STRUCT(, 0x00080000, 0x00080000),", + "_PAD_CFG_STRUCT(, 0x00040000, 0x00040000),", + "_PAD_CFG_STRUCT(, 0x00020000, 0x00020000),", + "_PAD_CFG_STRUCT(, 0x00010000, 0x00010000),", + "_PAD_CFG_STRUCT(, 0x00008000, 0x00008000),", + "_PAD_CFG_STRUCT(, 0x00004000, 0x00004000),", + "_PAD_CFG_STRUCT(, 0x00002000, 0x00002000),", + "_PAD_CFG_STRUCT(, 0x00001000, 0x00001000),", + "_PAD_CFG_STRUCT(, 0x00000800, 0x00000800),", + "_PAD_CFG_STRUCT(, 0x00000400, 0x00000400),", + "_PAD_CFG_STRUCT(, 0x00000200, 0x00000200),", + "_PAD_CFG_STRUCT(, 0x00000100, 0x00000100),", + "_PAD_CFG_STRUCT(, 0x00000080, 0x00000080),", + "_PAD_CFG_STRUCT(, 0x00000040, 0x00000040),", + "_PAD_CFG_STRUCT(, 0x00000020, 0x00000020),", + "_PAD_CFG_STRUCT(, 0x00000010, 0x00000010),", + "_PAD_CFG_STRUCT(, 0x00000008, 0x00000008),", + "_PAD_CFG_STRUCT(, 0x00000004, 0x00000004),", + "_PAD_CFG_STRUCT(, 0x00000002, 0x00000002),", + "_PAD_CFG_STRUCT(, 0x00000001, 0x00000001),", + } + test.SlidingOneTestSuiteCreate(referenceSlice).Run(t, "SLIDING-ONE-TEST", raw.FieldMacros{}) +} diff --git a/util/intelp2m/fields/test/suite.go b/util/intelp2m/fields/test/suite.go new file mode 100644 index 0000000..a61062e --- /dev/null +++ b/util/intelp2m/fields/test/suite.go @@ -0,0 +1,54 @@ +package test + +import ( + "fmt" + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/common" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" +) + +type TestCase struct { + DW0, DW1 uint32 + Ownership uint8 + Reference string +} + +func (tc TestCase) Check(actuallyMacro string) error { + if actuallyMacro != tc.Reference { + return fmt.Errorf(`TestCase: DW0 = %d, DW1 = %d, Ownership = %d: +Expects: '%s' +Actually: '%s'`, tc.DW0, tc.DW1, tc.Ownership, tc.Reference, actuallyMacro) + } + return nil +} + +type Suite []TestCase + +func (suite Suite) Run(t *testing.T, label string, decoderIf common.Fields) { + t.Run(label, func(t *testing.T) { + platform := snr.PlatformSpecific{} + macro := common.GetInstanceMacro(platform, decoderIf) + dw0 := macro.Register(common.PAD_CFG_DW0) + dw1 := macro.Register(common.PAD_CFG_DW1) + for _, tc := range suite { + macro.Clear() + macro.PadIdSet("").SetPadOwnership(tc.Ownership) + dw0.ValueSet(tc.DW0) + dw1.ValueSet(tc.DW1) + macro.Fields.GenerateString() + if err := tc.Check(macro.Get()); err != nil { + t.Errorf("Test failed: %v", err) + } + } + }) +} + +func SlidingOneTestSuiteCreate(referenceSlice []string) Suite { + suite := make([]TestCase, len(referenceSlice)) + dw := uint32(0x80000000) + for i, reference := range referenceSlice { + suite[i] = TestCase{DW0: dw >> i, DW1: dw >> i, Reference: reference} + } + return suite +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6330855b1c7463a3093b38c54e6cc06c3409009a Gerrit-Change-Number: 68673 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022