coreboot-gerrit October 2022

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[M] Change in coreboot[master]: arch/x86/include/arch: fix assembly clobber for 64bit
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66345 ) Change subject: arch/x86/include/arch: fix assembly clobber for 64bit ...................................................................... arch/x86/include/arch: fix assembly clobber for 64bit the "x86 PIC code ebx" workaround done previously by commit 689e31d18b0f ("Make cpuid functions usable when compiled with PIC") does not work for x86_64 (the upper dword of rbx is set to 0) the GCC bug that needed the workaround was fixed in version 5 (see GCC bug 54232) Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Signed-off-by: Matei Dibu <matdibu(a)protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66345 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/cpuid.h 1 file changed, 50 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/arch/x86/include/arch/cpuid.h b/src/arch/x86/include/arch/cpuid.h index 27848a8..70a5beb 100644 --- a/src/arch/x86/include/arch/cpuid.h +++ b/src/arch/x86/include/arch/cpuid.h @@ -15,96 +15,80 @@ /* * Generic CPUID function */ -static inline struct cpuid_result cpuid(int op) +static inline struct cpuid_result cpuid(const uint32_t eax) { struct cpuid_result result; asm volatile( - "mov %%ebx, %%edi;" "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" : "=a" (result.eax), - "=S" (result.ebx), + "=b" (result.ebx), "=c" (result.ecx), "=d" (result.edx) - : "0" (op) - : "edi"); + : "a" (eax)); return result; } /* * Generic Extended CPUID function */ -static inline struct cpuid_result cpuid_ext(int op, unsigned int ecx) +static inline struct cpuid_result cpuid_ext(const uint32_t eax, const uint32_t ecx) { struct cpuid_result result; asm volatile( - "mov %%ebx, %%edi;" "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" : "=a" (result.eax), - "=S" (result.ebx), + "=b" (result.ebx), "=c" (result.ecx), "=d" (result.edx) - : "0" (op), "2" (ecx) - : "edi"); + : "a" (eax), "c" (ecx)); return result; } /* * CPUID functions returning a single datum */ -static inline unsigned int cpuid_eax(unsigned int op) +static inline uint32_t cpuid_eax(uint32_t eax) { - unsigned int eax; - - __asm__("mov %%ebx, %%edi;" + asm volatile( "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax) - : "0" (op) - : "ecx", "edx", "edi"); + : "+a" (eax) + :: "ebx", "ecx", "edx"); return eax; } -static inline unsigned int cpuid_ebx(unsigned int op) +static inline uint32_t cpuid_ebx(const uint32_t eax) { - unsigned int eax, ebx; + uint32_t ebx; - __asm__("mov %%ebx, %%edi;" + asm volatile( "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=S" (ebx) - : "0" (op) - : "ecx", "edx", "edi"); + : "=b" (ebx) + : "a" (eax) + : "ecx", "edx"); return ebx; } -static inline unsigned int cpuid_ecx(unsigned int op) +static inline uint32_t cpuid_ecx(const uint32_t eax) { - unsigned int eax, ecx; + uint32_t ecx; - __asm__("mov %%ebx, %%edi;" + asm volatile( "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=c" (ecx) - : "0" (op) - : "edx", "edi"); + : "=c" (ecx) + : "a" (eax) + : "ebx", "edx"); return ecx; } -static inline unsigned int cpuid_edx(unsigned int op) +static inline uint32_t cpuid_edx(const uint32_t eax) { - unsigned int eax, edx; + uint32_t edx; - __asm__("mov %%ebx, %%edi;" + asm volatile( "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=d" (edx) - : "0" (op) - : "ecx", "edi"); + : "=d" (edx) + : "a" (eax) + : "ebx", "ecx"); return edx; } -- To view, visit https://review.coreboot.org/c/coreboot/+/66345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Gerrit-Change-Number: 66345 Gerrit-PatchSet: 11 Gerrit-Owner: Matei Dibu <matdibu(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M ...................................................................... mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases, such as emitting POST codes through a PCIe device. For the initialization to happen properly, certain register writes specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter 3.3.1 have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emitted before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_apl1/bootblock.c 1 file changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index a858f1b..7aab2a0 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -2,7 +2,26 @@ #include <baseboard/variants.h> #include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> #include <intelblocks/gpio.h> +#include <types.h> + +static void pcie_rp_early_enable(void) +{ + const pci_devfn_t rp_dev = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + if (pci_read_config16(rp_dev, PCI_VENDOR_ID) == 0xffff) + return; + + /* + * Needs to be done "immediately after PERST# de-assertion" + * as per IAFW BIOS spec volume 2 (doc 559811) + */ + pci_and_config32(rp_dev, 0x338, ~(1 << 26)); /* BLKDQDA */ + pci_and_config32(rp_dev, 0xf4, ~(1 << 2)); /* BLKPLLEN */ +} void bootblock_mainboard_early_init(void) { @@ -11,4 +30,8 @@ pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); + + /* Enable the PCIe root port when used before FSP-M MemoryInit() */ + if (CONFIG(EARLY_PCI_BRIDGE)) + pcie_rp_early_enable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68252 ) Change subject: soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control ...................................................................... soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control Enable the VCCST ICCMax Control for the ADL-N display flicker issue. Please refer the Doc with ID 742988 for more details. BUG=b:248249033 TEST=Verified that the display flicker issue is fixed. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Baieswara Reddy Sagili: Looks good to me, but someone else must approve Reka Norman: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5346403..dda2145 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1068,6 +1068,15 @@ s_cfg->PchFivrExtVnnRailIccMaximum = config->ext_fivr_settings.vnn_icc_max_ma; + +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + /* Enable the FIVR VCCST ICCMax Control for ADL-N. + * TODO:Right now the UPD is update in partial headers for only ADL-N and when its + * updated for ADL-P then we will remove the config since this needs to be enabled for + * all the Alderlake platforms. + */ + s_cfg->PchFivrVccstIccMaxControl = 1; +#endif } static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/68252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5 Gerrit-Change-Number: 68252 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ifdtool: Hardcode supported regions for every chipset
by build bot (Jenkins) (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68696 ) Change subject: ifdtool: Hardcode supported regions for every chipset ...................................................................... Patch Set 5: (3 comments) File util/ifdtool/regions.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161072): https://review.coreboot.org/c/coreboot/+/68696/comment/e557ab96_52f3a5b8 PS5, Line 57: [CHIPSET_300_SERIES_CANNON_POINT] = 0x11f, // CML SPI Programming Guide line length of 100 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161072): https://review.coreboot.org/c/coreboot/+/68696/comment/80dc5048_1a74874d PS5, Line 58: [CHIPSET_400_SERIES_ICE_POINT] = 0x11f, // ICL SPI Programming Guide line length of 100 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161072): https://review.coreboot.org/c/coreboot/+/68696/comment/e18ba6c2_2726dc39 PS5, Line 59: [CHIPSET_500_600_SERIES_TIGER_ALDER_POINT] = 0x11f, // TGL/ADL SPI Programming Guide line length of 104 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/68696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Gerrit-Change-Number: 68696 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 15:22:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ifdtool: Hardcode supported regions for every chipset
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68696 to look at the new patch set (#5). Change subject: ifdtool: Hardcode supported regions for every chipset ...................................................................... ifdtool: Hardcode supported regions for every chipset Hardcode the supported regions for every chipset. This allows to decide if a region is reserved and it allows to get the maximum number of regions per chipset. Update max_regions using the introduced array to prevent corruption of IFDs that have less than 16 regions. Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h M util/ifdtool/regions.c 3 files changed, 68 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/68696/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Gerrit-Change-Number: 68696 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: ifdtool: Drop chipset without IFD
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Stefan Reinauer, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68692 ) Change subject: ifdtool: Drop chipset without IFD ...................................................................... Patch Set 4: (1 comment) File util/ifdtool/ifdtool.h: https://review.coreboot.org/c/coreboot/+/68692/comment/907911b5_dbb11a9c PS2, Line 22: CHIPSET_ICH7, > this one too? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Gerrit-Change-Number: 68692 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 22 Oct 2022 14:59:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ifdtool: Hardcode supported regions for every chipset
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68696 to look at the new patch set (#4). Change subject: ifdtool: Hardcode supported regions for every chipset ...................................................................... ifdtool: Hardcode supported regions for every chipset Hardcode the supported regions for every chipset. This allows to decide if a region is reserved and it allows to get the maximum number of regions per chipset. Update max_regions using the introduced array to prevent corruption of IFDs that have less than 16 regions. Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h M util/ifdtool/regions.c 3 files changed, 68 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/68696/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Gerrit-Change-Number: 68696 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: ifdtool: Drop chipset without IFD
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68692 to look at the new patch set (#4). Change subject: ifdtool: Drop chipset without IFD ...................................................................... ifdtool: Drop chipset without IFD Drop unused chipsets that to not use an IFD. Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 12 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/68692/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Gerrit-Change-Number: 68692 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: ifdtool: Hardcode supported regions for every chipset
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68696 to look at the new patch set (#3). Change subject: ifdtool: Hardcode supported regions for every chipset ...................................................................... ifdtool: Hardcode supported regions for every chipset Hardcode the supported regions for every chipset. This allows to decide if a region is reserved and it allows to get the maximum number of regions per chipset. Update max_regions using the introduced array to prevent corruption of IFDs that have less than 16 regions. Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h M util/ifdtool/regions.c 3 files changed, 69 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/68696/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9757999cb2ab4b16a5352baacdc11c61164dd46 Gerrit-Change-Number: 68696 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: ifdtool: Move regions to seperate file
by Patrick Rudolph (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68695 to look at the new patch set (#3). Change subject: ifdtool: Move regions to seperate file ...................................................................... ifdtool: Move regions to seperate file Change-Id: I6a1ba1799c69881b1f48d903b8f86e7cd93815c2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/Makefile.inc M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h A util/ifdtool/regions.c 4 files changed, 169 insertions(+), 137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/68695/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a1ba1799c69881b1f48d903b8f86e7cd93815c2 Gerrit-Change-Number: 68695 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022