coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[S] Change in coreboot[master]: ifdtool: Add missing chipset_name
by Lean Sheng Tan (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68693 ) Change subject: ifdtool: Add missing chipset_name ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd8494123490d6ccc21af2ed30c30d50ddb4e8e Gerrit-Change-Number: 68693 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 17:24:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: ifdtool: Drop chipset without IFD
by Lean Sheng Tan (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68692 ) Change subject: ifdtool: Drop chipset without IFD ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb Gerrit-Change-Number: 68692 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 22 Oct 2022 17:24:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: ifdtool: Cleanup IFDv1 detection
by Lean Sheng Tan (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68680 ) Change subject: ifdtool: Cleanup IFDv1 detection ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10 Gerrit-Change-Number: 68680 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 17:23:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQ
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68638 ) Change subject: mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQ ...................................................................... mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQ The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects. Therefore, update the gpio.c to be consistent with the configuration. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Chao Gui <chaogui(a)google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Chao Gui: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index b44114e..6062d93 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -51,7 +51,7 @@ /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* SOC_FP_INT_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + PAD_SCI(GPIO_24, PULL_NONE, LEVEL_LOW), /* GPIO_25: Not available */ /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), -- To view, visit https://review.coreboot.org/c/coreboot/+/68638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Gerrit-Change-Number: 68638 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: payloads/edk2: Disable the CPU Timer Lib unless supported
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65950 ) Change subject: payloads/edk2: Disable the CPU Timer Lib unless supported ...................................................................... payloads/edk2: Disable the CPU Timer Lib unless supported For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M payloads/external/Makefile.inc M payloads/external/edk2/Kconfig M payloads/external/edk2/Makefile M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 13 files changed, 57 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 2c7337a..a2d2f50 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -164,6 +164,7 @@ CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \ CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \ CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \ + CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \ CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \ CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \ CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \ @@ -182,6 +183,7 @@ CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ + CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \ CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ @@ -203,6 +205,7 @@ CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \ CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \ CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \ + CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \ CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \ CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \ CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \ @@ -221,6 +224,7 @@ CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ + CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \ CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index e0c19bb..454aef0 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -155,6 +155,20 @@ this option, especially if using a debug (vs release) build. Selecting this option will increase the payload size in CBFS by 0x10000. +config EDK2_CPU_TIMER_LIB + bool + default n + help + For recent Intel and AMD CPUs, the 0x15 CPUID instruction will return Time + Stamp Counter Frequence. For CPUs that do not support this instruction, + EDK2 must include a different library which is the reason why this must be + configured at build time. + + If this is enabled, and the CPU doesn't support 0x15, it will fail to + boot. If it is not enabled, and the CPU does support 0x15, it will still + boot but without support for the leaf. Consequently, it is disabled by + default. + config EDK2_FOLLOW_BGRT_SPEC bool "Center logo 38.2% from the top of screen" default n diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index e1a0c93..ff1dfbc 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -44,6 +44,12 @@ else RELEASE_STR = RELEASE endif +# CPU_TIMER_LIB_ENABLE = TRUE +ifneq ($(CONFIG_EDK2_CPU_TIMER_LIB),y) +BUILD_STR += -D CPU_TIMER_LIB_ENABLE=FALSE +else +BUILD_STR += --pcd gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency=$(CONFIG_CPU_XTAL_HZ) +endif # DISABLE_SERIAL_TERMINAL = FALSE ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y) BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08a56c4..92a8c06 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -55,6 +55,7 @@ select CPU_SUPPORTS_PM_TIMER_EMULATION select DISPLAY_FSP_VERSION_INFO select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZ4 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b2c2246..fcde2ec 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -37,6 +37,7 @@ select SOC_INTEL_COMMON_NHLT # Misc options select CACHE_MRC_SETTINGS + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FAST_SPI_GENERATE_SSDT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_STATUS_GLOBAL_RESET_REQUIRED_5 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 2a66f8a..7755560 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -60,6 +60,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DISPLAY_FSP_VERSION_INFO + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 8544ac5..dcf9a5f 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DEBUG_GPIO + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_M_XIP select FSP_T_XIP if FSP_CAR select HAVE_INTEL_FSP_REPO diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 4af3276..4343e85 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -15,6 +15,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DISPLAY_FSP_VERSION_INFO + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1c64949..aca73fa 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -15,6 +15,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DISPLAY_FSP_VERSION_INFO + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index e2fc4e4..e7b486b 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -16,6 +16,7 @@ select CPU_SUPPORTS_PM_TIMER_EMULATION select COS_MAPPED_TO_MSB select DISPLAY_FSP_VERSION_INFO_2 + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 67d5bc1..9ef58aa 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -19,6 +19,7 @@ select DISPLAY_FSP_VERSION_INFO select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZ4 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index db957f2..e15af04 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -29,6 +29,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 5b09ed7..4d87192 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -20,6 +20,7 @@ select CPU_SUPPORTS_PM_TIMER_EMULATION select DISPLAY_FSP_VERSION_INFO if !FSP_TYPE_IOT select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP -- To view, visit https://review.coreboot.org/c/coreboot/+/65950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Gerrit-Change-Number: 65950 Gerrit-PatchSet: 36 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: payloads/edk2: Add the recipes to assemble UniversalPayload
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65932 ) Change subject: payloads/edk2: Add the recipes to assemble UniversalPayload ...................................................................... payloads/edk2: Add the recipes to assemble UniversalPayload Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Id6363c92f8155007e05c682694d7413fd4630b6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65932 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M payloads/external/Makefile.inc M payloads/external/edk2/Makefile 2 files changed, 57 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 70096f5..2c7337a 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -193,6 +193,45 @@ OBJCOPY_arm64=$(OBJCOPY_arm64) \ MFLAGS= MAKEFLAGS= +$(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG) + $(MAKE) -C payloads/external/edk2 UniversalPayload \ + HOSTCC="$(HOSTCC)" \ + CC="$(HOSTCC)" \ + CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \ + CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \ + CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \ + CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \ + CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \ + CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \ + CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \ + CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \ + CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \ + CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \ + CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \ + CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \ + CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \ + CONFIG_EDK2_CBMEM_LOGGING=$(CONFIG_EDK2_CBMEM_LOGGING) \ + CONFIG_EDK2_FOLLOW_BGRT_SPEC=$(CONFIG_EDK2_FOLLOW_BGRT_SPEC) \ + CONFIG_EDK2_FULL_SCREEN_SETUP=$(CONFIG_EDK2_FULL_SCREEN_SETUP) \ + CONFIG_EDK2_HAVE_EFI_SHELL=$(CONFIG_EDK2_HAVE_EFI_SHELL) \ + CONFIG_EDK2_PRIORITIZE_INTERNAL=$(CONFIG_EDK2_PRIORITIZE_INTERNAL) \ + CONFIG_EDK2_PS2_SUPPORT=$(CONFIG_EDK2_PS2_SUPPORT) \ + CONFIG_EDK2_SERIAL_SUPPORT=$(CONFIG_EDK2_SERIAL_SUPPORT) \ + CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \ + CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \ + CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ + CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ + CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \ + GCC_CC_x86_32=$(GCC_CC_x86_32) \ + GCC_CC_x86_64=$(GCC_CC_x86_64) \ + GCC_CC_arm=$(GCC_CC_arm) \ + GCC_CC_arm64=$(GCC_CC_arm64) \ + OBJCOPY_x86_32=$(OBJCOPY_x86_32) \ + OBJCOPY_x86_64=$(OBJCOPY_x86_64) \ + OBJCOPY_arm=$(OBJCOPY_arm) \ + OBJCOPY_arm64=$(OBJCOPY_arm64) \ + MFLAGS= MAKEFLAGS= + # FILO filo: diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 498e11a..e1a0c93 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -229,10 +229,14 @@ mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \ ../../../build/UEFIPAYLOAD.fd +UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll + mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \ + ../../../build/ShimmedUniversalPayload.elf + clean: test -d $(WORKSPACE) && (cd $(WORKSPACE); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 distclean: rm -rf $(WORKSPACE) -.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg clean distclean +.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg UniversalPayload clean distclean -- To view, visit https://review.coreboot.org/c/coreboot/+/65932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6363c92f8155007e05c682694d7413fd4630b6d Gerrit-Change-Number: 65932 Gerrit-PatchSet: 43 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/intel/systemagent: Rewrite using new resource API
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68406 ) Change subject: soc/intel/systemagent: Rewrite using new resource API ...................................................................... soc/intel/systemagent: Rewrite using new resource API Working with resources in KB is tedious and the base_k / size_k variable naming was simply wrong in one case. Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 23 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index dbc52c5..1938765 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -187,8 +187,6 @@ */ static void sa_add_dram_resources(struct device *dev, int *resource_count) { - uintptr_t base_k; - size_t size_k; uint64_t sa_map_values[MAX_MAP_ENTRIES]; uintptr_t top_of_ram; int index = *resource_count; @@ -196,21 +194,15 @@ top_of_ram = (uintptr_t)cbmem_top(); /* 0 - > 0xa0000 */ - base_k = 0; - size_k = (0xa0000 / KiB) - base_k; - ram_resource_kb(dev, index++, base_k, size_k); + ram_from_to(dev, index++, 0, 0xa0000); /* 0xc0000 -> top_of_ram */ - base_k = 0xc0000 / KiB; - size_k = (top_of_ram / KiB) - base_k; - ram_resource_kb(dev, index++, base_k, size_k); + ram_from_to(dev, index++, 0xc0000, top_of_ram); sa_get_mem_map(dev, &sa_map_values[0]); /* top_of_ram -> TOLUD */ - base_k = top_of_ram; - size_k = sa_map_values[SA_TOLUD_REG] - base_k; - reserved_ram_resource_kb(dev, index++, base_k / KiB, size_k / KiB); + reserved_ram_from_to(dev, index++, top_of_ram, sa_map_values[SA_TOLUD_REG]); /* 4GiB -> TOUUD */ upper_ram_end(dev, index++, sa_map_values[SA_TOUUD_REG]); @@ -221,9 +213,8 @@ * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM */ - mmio_resource_kb(dev, index++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); - reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB, - (1*MiB - 0xc0000) / KiB); + mmio_from_to(dev, index++, 0xa0000, 0xc0000); + reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); *resource_count = index; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904 Gerrit-Change-Number: 68406 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/intel/systemagent.c: Fix memory type reporting
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68405 ) Change subject: soc/intel/systemagent.c: Fix memory type reporting ...................................................................... soc/intel/systemagent.c: Fix memory type reporting TOLUD stands for top of lower usable dram. Memory between cbmem_top and TOLUD, even if stolen for another device/purpose can still be marked WB cacheable. This will result in a cleaner MTRR setup. Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Sean Rhodes: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index c2ce999..dbc52c5 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -210,7 +210,7 @@ /* top_of_ram -> TOLUD */ base_k = top_of_ram; size_k = sa_map_values[SA_TOLUD_REG] - base_k; - mmio_resource_kb(dev, index++, base_k / KiB, size_k / KiB); + reserved_ram_resource_kb(dev, index++, base_k / KiB, size_k / KiB); /* 4GiB -> TOUUD */ upper_ram_end(dev, index++, sa_map_values[SA_TOUUD_REG]); -- To view, visit https://review.coreboot.org/c/coreboot/+/68405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Gerrit-Change-Number: 68405 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/intel/systemagent.c: Fix memory type reporting
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Paul Menzel, Arthur Heymans. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68405 ) Change subject: soc/intel/systemagent.c: Fix memory type reporting ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68405/comment/fa8fa254_e7694865 PS2, Line 12: > Good point, I think this is resolved now as Angel has posted the log in comments. Agreed - it's a lot to put in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/68405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Gerrit-Change-Number: 68405 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 22 Oct 2022 16:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68666 ) Change subject: mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants ...................................................................... mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 69277a5..bc3c4a0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -126,6 +126,12 @@ register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1" + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index ecf5d55..4109ec9 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -117,6 +117,12 @@ }, }" + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/68666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Gerrit-Change-Number: 68666 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2022