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[M] Change in coreboot[master]: soc/intel/common: Clean up includes
by Elyes Haouas (Code Review) 22 Oct '22

22 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68702 ) Change subject: soc/intel/common: Clean up includes ...................................................................... soc/intel/common: Clean up includes Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/acpi/lpit.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/gpio/gpio_dev.c M src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/smbios.h M src/soc/intel/common/vbt.c 16 files changed, 44 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/68702/1 diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c index 5b9689c..38a402f 100644 --- a/src/soc/intel/common/block/acpi/lpit.c +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -4,6 +4,7 @@ #include <cpu/intel/msr.h> #include <soc/iomap.h> #include <soc/pmc.h> +#include <stdint.h> unsigned long acpi_fill_lpit(unsigned long current) { diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 21e3d35..cd1030c 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <acpi/acpigen.h> #include <assert.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> #include <intelblocks/acpi.h> #include <intelblocks/pmc_ipc.h> #include <stdlib.h> +#include <string.h> #include <types.h> #define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" diff --git a/src/soc/intel/common/block/gpio/gpio_dev.c b/src/soc/intel/common/block/gpio/gpio_dev.c index a179473..bea0363 100644 --- a/src/soc/intel/common/block/gpio/gpio_dev.c +++ b/src/soc/intel/common/block/gpio/gpio_dev.c @@ -3,8 +3,8 @@ #include <assert.h> #include <device/device.h> #include <device/gpio.h> -#include <intelblocks/gpio.h> #include <gpio.h> +#include <intelblocks/gpio.h> static struct gpio_operations gpio_ops = { .get = gpio_get, diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c index 1b2a2d1..cef2e57 100644 --- a/src/soc/intel/common/block/gpmr/gpmr.c +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -5,6 +5,7 @@ #include <intelblocks/ioc.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> +#include <types.h> /* GPMR Register read given offset */ uint32_t gpmr_read32(uint16_t offset) diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 63aa800..3093921 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -4,6 +4,7 @@ #define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H #include <device/device.h> +#include <stdint.h> /* * SoC overrides diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index d3fcbde..dd0b0ef 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <device/device.h> #include <device/pci.h> -#include <device/pciexp.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pciexp.h> +#include <stdint.h> #define CACHE_LINE_SIZE 0x10 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index ba49f7c..897cd82 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -2,13 +2,17 @@ #define __SIMPLE_DEVICE__ -#include <device/mmio.h> #include <assert.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> -#include <intelblocks/pcr.h> +#include <device/mmio.h> +#include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pci_type.h> +#include <intelblocks/pcr.h> #include <soc/pci_devs.h> #include <timer.h> +#include <types.h> #if (CONFIG_PCR_BASE_ADDRESS == 0) #error "PCR_BASE_ADDRESS need to be non-zero!" diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index a3173f3..273d29e 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -4,8 +4,11 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> +#include <device/pci_type.h> #include <intelblocks/smbus.h> #include <soc/pci_devs.h> +#include <stdint.h> + #include "smbuslib.h" void smbus_common_init(void) diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 7bdaada..f6a211b 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -2,17 +2,22 @@ #define __SIMPLE_DEVICE__ +#include <assert.h> +#include <commonlib/bsd/helpers.h> #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_type.h> #include <device/spi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> #include <soc/pci_devs.h> #include <spi-generic.h> +#include <types.h> const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 86ca4e1..97344cd 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -2,6 +2,7 @@ #include <arch/romstage.h> #include <cbmem.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index 81496ce..85292e2 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_device.h> #include <acpi/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/path.h> #include <string.h> + #include "chip.h" #define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 3300768..495996e 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -5,6 +5,7 @@ #include <device/pci_ids.h> #include <intelblocks/xdci.h> #include <security/vboot/vboot_common.h> +#include <stdbool.h> __weak void soc_xdci_init(struct device *dev) { /* no-op */ } diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c index e89fe4c..bf265515 100644 --- a/src/soc/intel/common/fsp_reset.c +++ b/src/soc/intel/common/fsp_reset.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <fsp/util.h> #include <soc/intel/common/reset.h> +#include <stdint.h> void chipset_handle_reset(uint32_t status) { diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 41ecac1..dceb031 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <delay.h> #include <device/azalia_device.h> #include <device/mmio.h> -#include <delay.h> +#include <stdint.h> #include "hda_verb.h" diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index c7da3b3..06a35c7 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -3,8 +3,8 @@ #ifndef _COMMON_SMBIOS_H_ #define _COMMON_SMBIOS_H_ -#include <stdint.h> #include <memory_info.h> +#include <types.h> /* Offset info DIMM_INFO SpdSave for start of serial number */ #define SPD_SAVE_OFFSET_SERIAL 5 diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 690fb5f..c01db66 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -2,9 +2,10 @@ #include <acpi/acpi.h> #include <bootmode.h> +#include <drivers/intel/gma/opregion.h> +#include <stddef.h> #include "vbt.h" -#include <drivers/intel/gma/opregion.h> void *vbt_get(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/68702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Gerrit-Change-Number: 68702 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/clevo/tgl-u: Clean up includes
by Elyes Haouas (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Felix Singer, Michael Niewöhner. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68701 ) Change subject: mb/clevo/tgl-u: Clean up includes ...................................................................... mb/clevo/tgl-u: Clean up includes Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c M src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68701/1 diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c index ebe499d..d8739a2 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/azalia_device.h> +#include <stdint.h> const u32 cim_verb_data[] = { /* Realtek ALC293 */ diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c index 14e81fe..a1cfb037 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/meminit.h> +#include <stdbool.h> #include <variant/romstage.h> void variant_configure_fspm(FSPM_UPD *memupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/68701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Gerrit-Change-Number: 68701 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/tigerlake: Clean up includes
by Elyes Haouas (Code Review) 22 Oct '22

22 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68700 ) Change subject: soc/intel/tigerlake: Clean up includes ...................................................................... soc/intel/tigerlake: Clean up includes Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/tigerlake/dptf.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/lockdown.c M src/soc/intel/tigerlake/me.c M src/soc/intel/tigerlake/p2sb.c M src/soc/intel/tigerlake/pcie_rp.c M src/soc/intel/tigerlake/retimer.c M src/soc/intel/tigerlake/romstage/systemagent.c M src/soc/intel/tigerlake/spi.c M src/soc/intel/tigerlake/xhci.c 12 files changed, 28 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/68700/1 diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index b8086a4..5ef9662 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <cpu/cpu.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <stdint.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/tigerlake/dptf.c b/src/soc/intel/tigerlake/dptf.c index 2f0427e..2f4cf5f 100644 --- a/src/soc/intel/tigerlake/dptf.c +++ b/src/soc/intel/tigerlake/dptf.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <drivers/intel/dptf/dptf.h> +#include <stdbool.h> static const struct dptf_platform_info tgl_dptf_platform_info = { .use_eisa_hids = false, diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 301c88a..29f1712 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <bootstate.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> +#include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pci_type.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <intelblocks/xhci.h> diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ef75c56..d7c60be 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -3,7 +3,6 @@ #include <assert.h> #include <console/console.h> #include <device/device.h> -#include <arch/pci_io_cfg.h> #include <cpu/intel/cpu_ids.h> #include <device/pci_ops.h> #include <device/pci.h> diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c index 1e04dc3..2f7cceb 100644 --- a/src/soc/intel/tigerlake/lockdown.c +++ b/src/soc/intel/tigerlake/lockdown.c @@ -10,6 +10,7 @@ #include <intelblocks/cfg.h> #include <intelpch/lockdown.h> #include <soc/pm.h> +#include <stdint.h> static void pmc_lock_pmsync(void) { diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index ea94902..560464f 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> -#include <intelblocks/cse.h> #include <console/console.h> +#include <intelblocks/cse.h> #include <soc/me.h> -#include <stdint.h> +#include <types.h> /* Host Firmware Status Register 2 */ union me_hfsts2 { diff --git a/src/soc/intel/tigerlake/p2sb.c b/src/soc/intel/tigerlake/p2sb.c index fc8323a..1a0f23f 100644 --- a/src/soc/intel/tigerlake/p2sb.c +++ b/src/soc/intel/tigerlake/p2sb.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <intelblocks/p2sb.h> +#include <types.h> void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) { diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c index 57a5cf2..01bca17 100644 --- a/src/soc/intel/tigerlake/pcie_rp.c +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <device/pci_def.h> #include <intelblocks/pcie_rp.h> #include <soc/pci_devs.h> +#include <stdbool.h> #define CPU_CPIE_VW_IDX_BASE 24 diff --git a/src/soc/intel/tigerlake/retimer.c b/src/soc/intel/tigerlake/retimer.c index 09bf112..32cb828 100644 --- a/src/soc/intel/tigerlake/retimer.c +++ b/src/soc/intel/tigerlake/retimer.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <drivers/intel/usb4/retimer/retimer.h> #include <intelblocks/tcss.h> +#include <stdint.h> int retimer_get_index_for_typec(uint8_t typec_port) { diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c index bedc192..2393e6a 100644 --- a/src/soc/intel/tigerlake/romstage/systemagent.c +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -6,6 +6,7 @@ * Chapter number: 3 */ +#include <commonlib/bsd/helpers.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/romstage.h> diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index d68b146..47b3b33 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -6,9 +6,10 @@ * Chapter number: 7 */ -#include <intelblocks/spi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/spi.h> #include <soc/pci_devs.h> +#include <stdint.h> #define PSF_SPI_DESTINATION_ID_H 0x23b0 #define PSF_SPI_DESTINATION_ID 0x23a8 diff --git a/src/soc/intel/tigerlake/xhci.c b/src/soc/intel/tigerlake/xhci.c index 6f095fa..af201aa 100644 --- a/src/soc/intel/tigerlake/xhci.c +++ b/src/soc/intel/tigerlake/xhci.c @@ -3,6 +3,7 @@ #include <device/pci_type.h> #include <intelblocks/xhci.h> #include <soc/pci_devs.h> +#include <stddef.h> #define PCH_XHCI_USB2_PORT_STATUS_REG 0x480 #define PCH_XHCI_USB3_PORT_STATUS_REG 0x520 -- To view, visit https://review.coreboot.org/c/coreboot/+/68700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Gerrit-Change-Number: 68700 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: treewide: Add 'IWYU pragma: export' comment
by Elyes Haouas (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Nico Huber, Martin L Roth, Angel Pons, Julius Werner, Kyösti Mälkki. Hello build bot (Jenkins), Nico Huber, Martin L Roth, Angel Pons, Julius Werner, Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68332 to look at the new patch set (#10). Change subject: treewide: Add 'IWYU pragma: export' comment ...................................................................... treewide: Add 'IWYU pragma: export' comment This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/cbmem.h M src/include/console/console.h M src/include/cpu/cpu.h M src/include/device/mmio.h M src/include/device/pci_ops.h M src/include/device/pnp.h M src/include/types.h M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 13 files changed, 28 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/68332/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/68332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Gerrit-Change-Number: 68332 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/systemagent: Rewrite using new resource API
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68406 ) Change subject: soc/intel/systemagent: Rewrite using new resource API ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130202 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130201 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130200 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130199 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130198 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130197 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130196 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130195 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130194 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130193 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130192 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130191 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130190 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130189 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130188 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130187 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904 Gerrit-Change-Number: 68406 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 19:27:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/systemagent.c: Fix memory type reporting
by 9elements QA (Code Review) 22 Oct '22

22 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68405 ) Change subject: soc/intel/systemagent.c: Fix memory type reporting ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 2 / 15 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130185 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130184 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130183 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130182 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130181 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130180 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130179 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130178 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130177 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130176 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130175 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130174 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130172 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130171 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130170 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Gerrit-Change-Number: 68405 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 18:34:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ifdtool: Use chipset to decide if region exists
by Elyes Haouas (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68697 ) Change subject: ifdtool: Use chipset to decide if region exists ...................................................................... Patch Set 5: (1 comment) File util/ifdtool/regions.c: https://review.coreboot.org/c/coreboot/+/68697/comment/fdd0c6d0_3de82ffa PS5, Line 181: 0 maybe "false" ? -- To view, visit https://review.coreboot.org/c/coreboot/+/68697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ac79f66395e378f45eba262df914478ff142b1f Gerrit-Change-Number: 68697 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 18:10:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ifdtool: Fix spacing for 10GbE_*
by Elyes Haouas (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68699 ) Change subject: ifdtool: Fix spacing for 10GbE_* ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie803df6ce9a9772116063ad20bad1c677c3b493c Gerrit-Change-Number: 68699 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Oct 2022 18:06:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs: Add skyrim config with binaries
by Jon Murphy (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Jason Glenesk, Martin L Roth. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68320 ) Change subject: configs: Add skyrim config with binaries ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31d11c5327416f4339930373c447531ae9f79d28 Gerrit-Change-Number: 68320 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Oct 2022 18:02:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd: Define AMD_FWM_POSITION config item
by Martin L Roth (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68584 ) Change subject: soc/amd: Define AMD_FWM_POSITION config item ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68584/comment/fb4b5ca0_e7e97d5f PS4, Line 11: Eventhough Nit: Even though https://review.coreboot.org/c/coreboot/+/68584/comment/4c633d49_e2069975 PS4, Line 12: we are not sure if : it is correct It's been working for a number of years now, so I don't think this is true. If you just put the 6 values into the formula, you can show that it's correct. It might be better to say that it's difficult to read, understand, maintain, etc. Patchset: PS4: Can we move this patch off of the patch train? It doesn't depend on the rest of the train, and having it in a train tends to keep it from being merged until everything earlier in the train is merged. This is really a general recommendation - Don't put things in a train unless required. File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/68584/comment/15a32650_6a654ee7 PS4, Line 60: default 5 if BOARD_ROMSIZE_KB_16384 Note that these are AMD's recommended defaults, but for ChromeOS, we won't want to use position 5 even when using a 16MiB chip because this is in the RW region. We might want to add a default for any google devices, then we can get rid of that setting from their Kconfig files. Obviously this could be done in a follow-on patch. https://review.coreboot.org/c/coreboot/+/68584/comment/b55c3f88_bf382388 PS4, Line 87: default 0xFFFA0000 if AMD_FWM_POSITION_INDEX = 0 : default 0xFFF20000 if AMD_FWM_POSITION_INDEX = 1 : default 0xFFE20000 if AMD_FWM_POSITION_INDEX = 2 : default 0xFFC20000 if AMD_FWM_POSITION_INDEX = 3 : default 0xFF820000 if AMD_FWM_POSITION_INDEX = 4 : default 0xFF020000 if AMD_FWM_POSITION_INDEX = 5 > Unfortunately amdfwtool expects it to be x86 memory mapped space. […] We also need to look ahead to 32 & 64MiB flash sizes and mapping the flash to the area over 4GiB so that we can access more than 16MiB at a time. That would also mean 64-bit coreboot builds. Obviously those are both larger tasks and not needed yet, though they might be needed on Morgana or Glinda platforms. -- To view, visit https://review.coreboot.org/c/coreboot/+/68584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4978a922744982afb231f8a9c650eedf950a507b Gerrit-Change-Number: 68584 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 22 Oct 2022 17:41:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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