coreboot-gerrit October 2022

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[S] Change in coreboot[master]: mainboard/msi/ms7d25: Configure NCT6687D pin for PECI
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68711 ) Change subject: mainboard/msi/ms7d25: Configure NCT6687D pin for PECI ...................................................................... mainboard/msi/ms7d25: Configure NCT6687D pin for PECI One register configuring multi-pin functions was outside of the Global Configuration Regisers space and skipped in the initial port patches. Replicate the vendor configuration and set the Super I/O pin for PECI functionality. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b --- M src/mainboard/msi/ms7d25/bootblock.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/68711/1 diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c index 2dcb763..110d682 100644 --- a/src/mainboard/msi/ms7d25/bootblock.c +++ b/src/mainboard/msi/ms7d25/bootblock.c @@ -6,6 +6,7 @@ #include <superio/nuvoton/nct6687d/nct6687d.h> #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) void bootblock_mainboard_early_init(void) { @@ -13,6 +14,8 @@ nuvoton_pnp_enter_conf_state(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + + /* Below are multi-pin function */ pnp_write_config(SERIAL_DEV, 0x15, 0xaa); pnp_write_config(SERIAL_DEV, 0x1a, 0x02); pnp_write_config(SERIAL_DEV, 0x1b, 0x02); @@ -31,7 +34,12 @@ pnp_write_config(SERIAL_DEV, 0x2b, 0x20); pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); - nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x80); + + nuvoton_pnp_exit_conf_state(POWER_DEV); if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -- To view, visit https://review.coreboot.org/c/coreboot/+/68711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b Gerrit-Change-Number: 68711 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Felix Held. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68710 ) Change subject: util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo ...................................................................... util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the patch adding register definitions for NCT6687D Super I/O chip. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca --- M util/superiotool/nuvoton.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/68710/1 diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 66dcfce..ea11393 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -90,7 +90,7 @@ {0xff,0xff,0x00,0x00,0x00,0x00,0x10,0x00,0x00, 0x00,0xd5,0x92,0x00,0x80,0x67,0x01,0x00,0x3e, 0x00,0x03,0x0f,0x00,0x00,0x00,MISC,EOT}}, - {0x02, "Parallel Port", + {0x01, "Parallel Port", {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x3f,EOT}}, {0x02, "UART A", -- To view, visit https://review.coreboot.org/c/coreboot/+/68710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca Gerrit-Change-Number: 68710 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mainboard/msi/ms7d25: Add support for DDR5 variant
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Kopeć. Hello build bot (Jenkins), Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68448 to look at the new patch set (#2). Change subject: mainboard/msi/ms7d25: Add support for DDR5 variant ...................................................................... mainboard/msi/ms7d25: Add support for DDR5 variant The DDR5 board is almost identical to the DDR4 one. The only major difference is the board's DDR5 memory design. TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I652a879d1616df4708fe4690797ad98384897f53 --- M configs/config.msi_ms7d25 A configs/config.msi_ms7d25_ddr4 M src/mainboard/msi/ms7d25/Kconfig M src/mainboard/msi/ms7d25/Kconfig.name M src/mainboard/msi/ms7d25/mainboard.c M src/mainboard/msi/ms7d25/romstage_fsp_params.c 6 files changed, 71 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/68448/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Gerrit-Change-Number: 68448 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: MAINTAINERS: Update instructions
by Martin L Roth (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68705 ) Change subject: MAINTAINERS: Update instructions ...................................................................... Patch Set 2: (1 comment) File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/68705/comment/fbc46a52_99a91638 PS1, Line 41: are be made > "are made"? Seems reasonable. -- To view, visit https://review.coreboot.org/c/coreboot/+/68705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e06ac5f92109757143897f3d331aeea0cefe4b9 Gerrit-Change-Number: 68705 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 23 Oct 2022 14:47:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Set the correct serial settings for AMD SOCs
by Matt DeVillier (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Sean Rhodes, Martin L Roth, Stefan Reinauer, Arthur Heymans. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68596 ) Change subject: payloads/edk2: Set the correct serial settings for AMD SOCs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Why is this needed? […] because you don't get serial output on Picasso (and forward) without it -- To view, visit https://review.coreboot.org/c/coreboot/+/68596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70630d21bbdb21f2aa8cbaeb3e842629b97af3ba Gerrit-Change-Number: 68596 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 23 Oct 2022 14:41:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Add STB Spill-to-DRAM enum
by Martin L Roth (Code Review) 23 Oct '22

23 Oct '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68686 ) Change subject: soc/amd/mendocino: Add STB Spill-to-DRAM enum ...................................................................... soc/amd/mendocino: Add STB Spill-to-DRAM enum This is the enum value to initialize the Smart Trace Buffer's Spill-to-DRAM feature. More information on how this is used is available in the STB Linux kernel driver. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/mendocino/include/soc/smu.h 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/mendocino/include/soc/smu.h b/src/soc/amd/mendocino/include/soc/smu.h index c2c629e..b811aca 100644 --- a/src/soc/amd/mendocino/include/soc/smu.h +++ b/src/soc/amd/mendocino/include/soc/smu.h @@ -12,6 +12,7 @@ enum smu_message_id { SMC_MSG_S3ENTRY = 0x0b, + SMC_MSG_SET_S2D_ADDR = 0x53, }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/68686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 Gerrit-Change-Number: 68686 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/clevo/tgl-u: Avoid indirect includes
by Elyes Haouas (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Felix Singer, Elyes Haouas. Hello Felix Singer, build bot (Jenkins), Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68701 to look at the new patch set (#5). Change subject: mb/clevo/tgl-u: Avoid indirect includes ...................................................................... mb/clevo/tgl-u: Avoid indirect includes Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c M src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68701/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Gerrit-Change-Number: 68701 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/clevo/tgl-u: Avoid indirect includes Change-Id: I51ab987420e592ac2...
by Elyes Haouas (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Felix Singer, Elyes Haouas. Hello Felix Singer, build bot (Jenkins), Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68701 to look at the new patch set (#4). Change subject: mb/clevo/tgl-u: Avoid indirect includes Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> ...................................................................... mb/clevo/tgl-u: Avoid indirect includes Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c M src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68701/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Gerrit-Change-Number: 68701 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: [UNTESTED]mainboard/msi/ms7d25: Add support for DDR5 variant
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68448 ) Change subject: [UNTESTED]mainboard/msi/ms7d25: Add support for DDR5 variant ...................................................................... Patch Set 1: (1 comment) File src/mainboard/msi/ms7d25/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/68448/comment/4dac3347_f3ecf01f PS1, Line 23: .type = MEM_TYPE_DDR5, > If this is the only functional difference between the boards, I wonder if there's a GPIO we could us […] We do not have any schematics so how would you find such GPIO? Better way would be to parse SPD and check the DDR technology, but parsing DDR5 SPD is not yet supported by coreboot AFAIK -- To view, visit https://review.coreboot.org/c/coreboot/+/68448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Gerrit-Change-Number: 68448 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Sun, 23 Oct 2022 09:17:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: MAINTAINERS: Update EC section
by Michael Niewöhner (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Martin L Roth. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68708 ) Change subject: MAINTAINERS: Update EC section ...................................................................... Patch Set 1: (1 comment) File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/68708/comment/81ec746c_83185618 PS1, Line 730: Orphaned ECs IMO "orphaned" could be misleading. What about "unmaintained" or "not actively maintained"? -- To view, visit https://review.coreboot.org/c/coreboot/+/68708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia93e8da9898903ae92873a07fb0af2a2aa76e8b4 Gerrit-Change-Number: 68708 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Oct 2022 08:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022