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Change subject: mb/clevo/tgl-u: Add missing includes
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68701/comment/cdda43f5_4201df9e
PS1, Line 7: Clean up includes
> Done
Well, IMO "Add missing includes" is not technically correct, since with missing includes that code wouldn't build. That's why my suggestion was "avoid indirect includes"
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Change subject: util/ifdtool: Add Wellsburg support
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Patch Set 3: Code-Review-1
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PS3:
It looks like some documents are wrong. Needs more tests on real hardware.
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Change subject: ifdtool: Hardcode supported regions for every chipset
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Patch Set 5: Code-Review-1
(1 comment)
Patchset:
PS5:
It looks like some documents are wrong. Needs more tests on real hardware.
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Change subject: MAINTAINERS: Update instructions
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Patch Set 1:
(1 comment)
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/68705/comment/927d31f5_fb8fda86
PS1, Line 41: are be made
"are made"?
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Hello Felix Singer, build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68701
to look at the new patch set (#3).
Change subject: mb/clevo/tgl-u: Add missing includes
......................................................................
mb/clevo/tgl-u: Add missing includes
Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c
M src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68701/3
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Change subject: payloads/edk2: Set the correct serial settings for AMD SOCs
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Why is this needed?
UefiPayloadPkg/Library/CbSerialPortLib/CbSerialPortLib.c should get this from coreboot tables.
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Change subject: soc/amd: Define AMD_FWM_POSITION config item
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/block/psp/Kconfig:
https://review.coreboot.org/c/coreboot/+/68584/comment/ee15ea25_b76b32a5
PS4, Line 87: default 0xFFFA0000 if AMD_FWM_POSITION_INDEX = 0
: default 0xFFF20000 if AMD_FWM_POSITION_INDEX = 1
: default 0xFFE20000 if AMD_FWM_POSITION_INDEX = 2
: default 0xFFC20000 if AMD_FWM_POSITION_INDEX = 3
: default 0xFF820000 if AMD_FWM_POSITION_INDEX = 4
: default 0xFF020000 if AMD_FWM_POSITION_INDEX = 5
> Unfortunately amdfwtool expects it to be x86 memory mapped space. There seems to be an assumption that the the last 16MB (0xff000000 - 0xffffffff) in the x86 32 bit memory map is where the SPI flash is present even if it's size is 16 MB or not. So it has to be an offset in that 16 MB. I will look for a best way to change it.
That is not true. Only MIN(16MB, CONFIG_ROM_SIZE) gets mapped. The PSP looks for the cookie on fixed addresses in flash space: 0x20000, 0x820000, 0xC20000, 0xE20000, 0xF20000, 0xFA0000. Where that is in memory map depends therefore on CONFIG_ROM_SIZE.
> We also need to look ahead to 32 & 64MiB flash sizes and mapping the flash to the area over 4GiB so that we can access more than 16MiB at a time. That would also mean 64-bit coreboot builds.
> Obviously those are both larger tasks and not needed yet, though they might be needed on Morgana or Glinda platforms.
Only 16MB gets memory mapped. When the flash size is for instance 32M, only the lower (by default) or the upper part of the flash gets memory mapped.
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Change subject: mb/clevo/tgl-u: Avoid indirect includes
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68701/comment/0e575b20_04f60c6b
PS1, Line 7: Clean up includes
> hm, is that really "cleaning up"? what about sth like "avoid indirect includes"?
Done
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