coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/mediatek: Move DP drivers to common
by Yu-Ping Wu (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68484 ) Change subject: soc/mediatek: Move DP drivers to common ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4 Gerrit-Change-Number: 68484 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 02:05:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Yu-Ping Wu (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68659/comment/b09e44cb_1ffb47f4 PS4, Line 13: This adds XXms to boot time. Patchset: PS4: Waiting for ODM to check the signal integrity of 39-MHz SPI. Keep this open. -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 01:59:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Yu-Ping Wu (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 01:57:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Yu-Ping Wu (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 01:57:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/acpi: Expand 5 DPTC thermal profiles support for Alib
by EricKY Cheng (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, EricKY Cheng, Matt DeVillier, Chris Wang, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Tim Van Patten, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68470 to look at the new patch set (#11). Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles support for Alib ...................................................................... soc/amd/acpi: Expand 5 DPTC thermal profiles support for Alib Update acpigen_write_alib_dptc() to support extra 5 thermal profiles User can use these profiles for their specific feature. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 --- M src/soc/amd/common/block/acpi/alib.c M src/soc/amd/common/block/include/amdblocks/alib.h 2 files changed, 111 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68470/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/68470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Gerrit-Change-Number: 68470 Gerrit-PatchSet: 11 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify PL2 setting to 25w
by Tyler Wang (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Reka Norman, Vidya Gopalakrishnan, Peter Ou. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68523 ) Change subject: mb/google/nissa/var/craask: Modify PL2 setting to 25w ...................................................................... Patch Set 4: (3 comments) This change is ready for review. File src/mainboard/google/brya/variants/craask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68523/comment/82f3dc46_c8680526 PS3, Line 145: 3000 > Hi Peter, Agreed to keep PL1_min at 5. […] Done, thanks! https://review.coreboot.org/c/coreboot/+/68523/comment/ebccd518_a03ecfa4 PS3, Line 148: 32 > Yes, this value is default setting in CB, we can fixed the number to 28. Done, thanks! https://review.coreboot.org/c/coreboot/+/68523/comment/3835290b_c033c9dd PS3, Line 154: .time_window_min = 28 * MSECS_PER_SEC, > Yes, will change the setting to 0 secs. Done, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/68523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 Gerrit-Change-Number: 68523 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 01:53:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Comment-In-Reply-To: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
by Eric Lai (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Subrata Banik, Selma Bensaid, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68635 ) Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Gerrit-Change-Number: 68635 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 01:19:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable RFIM for CNVi
by Eric Lai (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Tarun Tuli, John Zhao, Tim Wawrzynczak, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67791 ) Change subject: mb/google/rex: Enable RFIM for CNVi ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22f9861452c2c222dd7a33bfeb02c63b026bf2f7 Gerrit-Change-Number: 67791 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 01:16:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo
by Felix Singer (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Żygowski, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68710 ) Change subject: util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca Gerrit-Change-Number: 68710 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 23 Oct 2022 18:35:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard/msi/ms7d25: Add support for DDR5 variant
by Felix Singer (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68448 ) Change subject: mainboard/msi/ms7d25: Add support for DDR5 variant ...................................................................... Patch Set 2: (1 comment) File src/mainboard/msi/ms7d25/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/68448/comment/e9167d56_e1a4dfd2 PS2, Line 71: if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) : memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); : if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI)) : memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); How about adding two additional Kconfig options for DDR4 / DDR5 to the mainboard Kconfig? This scales much better when more variants are added. In mainboard `Kconfig`: ``` if BOARD_MSI_MS7D25 config HAS_MEMORY_DDR4 default n default y if BOARD_MSI_Z690_A_PRO_WIFI_DDR4 config HAS_MEMORY_DDR5 default n default y if BOARD_MSI_Z690_A_PRO_WIFI endif ``` Here, in `romstage_fsp_params.c`: ``` if (CONFIG(HAS_MEMORY_DDR4)) memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); if (CONFIG(HAS_MEMORY_DDR5)) memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/68448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Gerrit-Change-Number: 68448 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Sun, 23 Oct 2022 18:33:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022