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[M] Change in coreboot[master]: NOTFORMERGE/WIP/POC Use FDT as payload handoff instead lb_tables
by Arthur Heymans (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Martin L Roth, Stefan Reinauer. Hello Martin L Roth, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68719 to look at the new patch set (#2). Change subject: NOTFORMERGE/WIP/POC Use FDT as payload handoff instead lb_tables ...................................................................... NOTFORMERGE/WIP/POC Use FDT as payload handoff instead lb_tables Pass information to the payload via FDT instead of coreboot tables. Currently implemented: - usable / reserved memory - framebuffer (TODO: more formats) - Some CBMEM pointers TODO: clean up, add more entries, remove hacks Change-Id: Id96d4e7805855d35392e78f8d7b3a1ff911105a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/tianocore/tools_def.txt M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/include/boot/tables.h M src/include/bootmem.h M src/include/device_tree.h M src/include/fit.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/bootmem.c M src/lib/device_tree.c A src/lib/fdt_handoff.c M src/lib/fit.c M src/lib/fit_payload.c M src/lib/hardwaremain.c M src/lib/hexdump.c M src/lib/selfboot.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/mainboard.c 18 files changed, 212 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/68719/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96d4e7805855d35392e78f8d7b3a1ff911105a3 Gerrit-Change-Number: 68719 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: NOTFORMERGE/WIP/POC edk2 devicetree
by build bot (Jenkins) (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Martin L Roth, Stefan Reinauer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68719 ) Change subject: NOTFORMERGE/WIP/POC edk2 devicetree ...................................................................... Patch Set 1: (7 comments) File src/lib/device_tree.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161099): https://review.coreboot.org/c/coreboot/+/68719/comment/4cc9e4a1_8175aaf0 PS1, Line 148: printk(BIOS_DEBUG, "/memreserve/ 0x%016llx 0x%016llx\n", reserved_entry->start, reserved_entry->size); line length of 121 exceeds 96 columns File src/lib/fit_payload.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161099): https://review.coreboot.org/c/coreboot/+/68719/comment/b9e11cce_394980b1 PS1, Line 113: static const char *framebuffer_path[] = {"framebuffer", NULL}; static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161099): https://review.coreboot.org/c/coreboot/+/68719/comment/0d10a7df_51b5270a PS1, Line 115: framebuffer_path, &addr_cells, &size_cells, 1); line length of 112 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161099): https://review.coreboot.org/c/coreboot/+/68719/comment/3ad9d65e_6cbfac02 PS1, Line 212: {CBMEM_ID_WIFI_CALIBRATION, "coreboot-wifi-calibration", "coreboot-wifi-calibration"}, line length of 102 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161099): https://review.coreboot.org/c/coreboot/+/68719/comment/210c8dc8_6046afe5 PS1, Line 220: const struct cbmem_entry *cbmem_entry = cbmem_entry_find(sections_ids[i].cbmem_id); line length of 99 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161099): https://review.coreboot.org/c/coreboot/+/68719/comment/0c83e3bd_40452f5e PS1, Line 226: const char *node_path[] = { sections_ids[i].dt_node, NULL}; char * array declaration might be better as static const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161099): https://review.coreboot.org/c/coreboot/+/68719/comment/566174db_3ffc4241 PS1, Line 231: dt_add_reg_prop(dt_node, &section_base, &section_size, 1, addr_cells, size_cells); line length of 98 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/68719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96d4e7805855d35392e78f8d7b3a1ff911105a3 Gerrit-Change-Number: 68719 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Oct 2022 16:54:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: NOTFORMERGE/WIP/POC edk2 devicetree
by Arthur Heymans (Code Review) 23 Oct '22

23 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68719 ) Change subject: NOTFORMERGE/WIP/POC edk2 devicetree ...................................................................... NOTFORMERGE/WIP/POC edk2 devicetree Pass information to the payload via FDT instead of coreboot tables. Currently implemented: - usable / reserved memory - framebuffer (TODO: more formats) - Some CBMEM pointers TODO: clean up, add more entries, remove hacks Change-Id: Id96d4e7805855d35392e78f8d7b3a1ff911105a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/tianocore/tools_def.txt M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/include/boot/tables.h M src/include/bootmem.h M src/include/device_tree.h M src/include/fit.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/bootmem.c M src/lib/device_tree.c A src/lib/fdt_handoff.c M src/lib/fit.c M src/lib/fit_payload.c M src/lib/hardwaremain.c M src/lib/hexdump.c M src/lib/selfboot.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/mainboard.c 18 files changed, 212 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/68719/1 diff --git a/payloads/external/tianocore/tools_def.txt b/payloads/external/tianocore/tools_def.txt index fba9b09..5aced20 100755 --- a/payloads/external/tianocore/tools_def.txt +++ b/payloads/external/tianocore/tools_def.txt @@ -104,10 +104,10 @@ *_COREBOOT_X64_OBJCOPY_FLAGS = *_COREBOOT_X64_NASM_FLAGS = -f elf64 - DEBUG_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os + DEBUG_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-dangling-pointer DEBUG_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os -RELEASE_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable +RELEASE_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable -Wno-dangling-pointer RELEASE_COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) -flto -Os NOOPT_COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) -O0 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 0cf9c7f..80d658d 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -82,6 +82,7 @@ #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 #define CBMEM_ID_TYPE_C_INFO 0x54595045 #define CBMEM_ID_MEM_CHIP_INFO 0x5048434D +#define CBMEM_ID_FDT_HANDOFF 0x46445448 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -156,6 +157,7 @@ { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ { CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \ { CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \ - { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ - { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"} + { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}, \ + { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"}, \ + { CBMEM_ID_FDT_HANDOFF, "FDT HANDOFF"} #endif /* _CBMEM_ID_H_ */ diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index b440c8b..bfd6e3b 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -11,6 +11,13 @@ void *write_tables(void); /* + * Write architecture specific tables as well as the common + * info in flattened devicetree. + * Returns a pointer to the flattened devicetree or NULL on error. + */ +void *write_fdt_handoff(void); + +/* * Allow per-architecture table writes called from write_tables(). The * coreboot_table parameter provides a reference to where the coreboot * table will be written. The parameter is to allow architectures to diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 6ccdd88..82da6c6 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -55,6 +55,9 @@ /* Platform hook to add bootmem areas the platform / board controls. */ void bootmem_platform_add_ranges(void); +/* Initialize bootmem ranges */ +void bootmem_init(void); + /* Add a range of a given type to the bootmem address space. */ void bootmem_add_range(uint64_t start, uint64_t size, const enum bootmem_type tag); diff --git a/src/include/device_tree.h b/src/include/device_tree.h index ae30c59..0d27c33 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -86,6 +86,8 @@ struct device_tree_node *root; }; +void fdt_print_reserved(struct device_tree *tree); + /* * Flattened device tree functions. These generally return the number of bytes * which were consumed reading the requested value. diff --git a/src/include/fit.h b/src/include/fit.h index a1e970d..ae90c0d 100644 --- a/src/include/fit.h +++ b/src/include/fit.h @@ -56,6 +56,11 @@ */ void fit_update_memory(struct device_tree *tree); +void fit_add_default_compat_strings(void); + +void add_cb_fdt_data(struct device_tree *tree); +void add_fb_fdt(struct device_tree *tree); + /* * Do architecture specific payload placements and fixups. * Set entrypoint and first argument (if any). diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 0142300..f9c4cc0 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -114,3 +114,17 @@ in the background before they are actually required. This feature depends on the read-only boot_device having a DMA controller to perform the background transfer. + +config COREBOOT_TABLES + bool + default y + help + Select this to generate the coreboot tables as payload handoff + structure. + +config FDT_PAYLOAD_HANDOFF + bool + default n + select FLATTENED_DEVICE_TREE + help + Create a payload handoff in the flattened devicetree format. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 68a2960..480a911 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -128,6 +128,7 @@ ramstage-y += hardwaremain.c ramstage-y += selfboot.c ramstage-y += coreboot_table.c +ramstage-$(CONFIG_FDT_PAYLOAD_HANDOFF) += fdt_handoff.c ramstage-y += bootmem.c ramstage-y += fmap.c ramstage-y += memchr.c @@ -157,8 +158,8 @@ ramstage-y += b64_decode.c ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c -ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c -ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c +ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += fit.c +ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += fit_payload.c romstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 078f9609..9dc1eb5 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -56,7 +56,7 @@ } } -static void bootmem_init(void) +void bootmem_init(void) { const unsigned long cacheable = IORESOURCE_CACHEABLE; const unsigned long reserved = IORESOURCE_RESERVE; diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index b846c25..374a735 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -2,6 +2,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> +#include <stdbool.h> #include <commonlib/stdlib.h> #include <console/console.h> #include <ctype.h> @@ -72,8 +73,11 @@ static void print_property(const struct fdt_property *prop, int depth) { - int is_string = prop->size > 0 && - ((char *)prop->data)[prop->size - 1] == '\0'; + bool is_string = prop->size > 0 && + ((char *)prop->data)[prop->size - 1] == '\0'; + + if (!strcmp(prop->name, "reg")) + is_string = false; if (is_string) for (const char *c = prop->data; *c != '\0'; c++) @@ -136,7 +140,13 @@ print_flat_node(blob, offset, 0); } +void fdt_print_reserved(struct device_tree *tree) +{ + struct device_tree_reserve_map_entry *reserved_entry; + list_for_each(reserved_entry, tree->reserve_map, list_node) + printk(BIOS_DEBUG, "/memreserve/ 0x%016llx 0x%016llx\n", reserved_entry->start, reserved_entry->size); +} /* * A utility function to skip past nodes in flattened trees. diff --git a/src/lib/fdt_handoff.c b/src/lib/fdt_handoff.c new file mode 100644 index 0000000..e8b6eb0 --- /dev/null +++ b/src/lib/fdt_handoff.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <lib.h> +#include <cbmem.h> +#include <endian.h> +#include <boot/tables.h> +#include <fit.h> + +void *write_fdt_handoff(void) +{ + struct fdt_header header = {}; + header.magic = htobe32(FDT_HEADER_MAGIC); + header.reserve_map_offset = htobe32(sizeof(struct fdt_header)); + header.version = htobe32(FDT_SUPPORTED_VERSION); + header.last_comp_version = htobe32(FDT_SUPPORTED_VERSION - 1); + + struct device_tree tree = {}; + tree.header = &header; + tree.header_size = sizeof(struct fdt_header); + + struct device_tree_node root_node = { + .name = "" + }; + dt_add_u32_prop(&root_node, "#address-cells", 2); + dt_add_u32_prop(&root_node, "#size-cells", 2); + tree.root = &root_node; + + fit_add_default_compat_strings(); + + add_cb_fdt_data(&tree); + + bootmem_init(); + bootmem_dump_ranges(); + fit_update_memory(&tree); + + add_fb_fdt(&tree); + fdt_print_reserved(&tree); + dt_print_node(tree.root); + + /* convert the tree to a flat dt */ + void *dt = cbmem_add(CBMEM_ID_FDT_HANDOFF, dt_flat_size(&tree)); + dt_flatten(&tree, dt); + hexdump(dt, dt_flat_size(&tree)); + return dt; +} diff --git a/src/lib/fit.c b/src/lib/fit.c index 0513950..ee14ac0 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -35,7 +35,7 @@ return str; } -static void fit_add_default_compat_strings(void) +void fit_add_default_compat_strings(void) { char compat_string[80] = {}; diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 21bc4e8..d5d68b2 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -102,11 +102,41 @@ return fdt_unflatten(data); } +void add_fb_fdt(struct device_tree *tree) +{ + struct lb_framebuffer fb = {}; + if (!CONFIG(LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) + return; + + u32 addr_cells = 1, size_cells = 1; + + static const char *framebuffer_path[] = {"framebuffer", NULL}; + struct device_tree_node *framebuffer_node = dt_find_node(tree->root, + framebuffer_path, &addr_cells, &size_cells, 1); + dt_add_string_prop(framebuffer_node, "compatible", "simple-framebuffer"); + uint64_t phys_base = fb.physical_address; + uint64_t phys_size = fb.y_resolution * fb.bytes_per_line; + dt_add_reg_prop(framebuffer_node, &phys_base, &phys_size, 1, addr_cells, size_cells); + dt_add_u32_prop(framebuffer_node, "width", fb.x_resolution); + dt_add_u32_prop(framebuffer_node, "height", fb.y_resolution); + dt_add_u32_prop(framebuffer_node, "stride", fb.bytes_per_line); + dt_add_u32_prop(framebuffer_node, "height", fb.y_resolution); + + if (fb.red_mask_pos == 0 && fb.red_mask_size == 8 && + fb.green_mask_pos == 8 && fb.green_mask_size == 8 && + fb.blue_mask_pos == 16 && fb.blue_mask_size == 8) + dt_add_string_prop(framebuffer_node, "format", "a8b8g8r8"); + else if (fb.red_mask_pos == 16 && fb.red_mask_size == 8 && + fb.green_mask_pos == 8 && fb.green_mask_size == 8 && + fb.blue_mask_pos == 0 && fb.blue_mask_size == 8) + dt_add_string_prop(framebuffer_node, "format", "x8r8g8b8"); +} + /** * Add coreboot tables, CBMEM information and optional board specific strapping * IDs to the device tree loaded via FIT. */ -static void add_cb_fdt_data(struct device_tree *tree) +void add_cb_fdt_data(struct device_tree *tree) { u32 addr_cells = 1, size_cells = 1; u64 reg_addrs[2], reg_sizes[2]; @@ -119,6 +149,9 @@ /* Need to add 'ranges' to the intermediate node to make 'reg' work. */ dt_add_bin_prop(firmware_node, "ranges", NULL, 0); + dt_add_u32_prop(firmware_node, "#address-cells", 2); + dt_add_u32_prop(firmware_node, "#size-cells", 2); + static const char *coreboot_path[] = {"coreboot", NULL}; struct device_tree_node *coreboot_node = dt_find_node(firmware_node, @@ -128,15 +161,19 @@ /* Fetch CB tables from cbmem */ void *cbtable = cbmem_find(CBMEM_ID_CBTABLE); - if (!cbtable) { + if (!cbtable && CONFIG(COREBOOT_TABLES)) { printk(BIOS_WARNING, "FIT: No coreboot table found!\n"); return; - } + } else if (!cbtable) { + reg_addrs[0] = 0; + reg_sizes[0] = 0; - /* First 'reg' address range is the coreboot table. */ - const struct lb_header *header = cbtable; - reg_addrs[0] = (uintptr_t)header; - reg_sizes[0] = header->header_bytes + header->table_bytes; + } else { + /* First 'reg' address range is the coreboot table. */ + const struct lb_header *header = cbtable; + reg_addrs[0] = (uintptr_t)header; + reg_sizes[0] = header->header_bytes + header->table_bytes; + } /* Second is the CBMEM area (which usually includes the coreboot table). */ @@ -161,6 +198,38 @@ if (ram_code() != UNDEFINED_STRAPPING_ID) dt_add_u32_prop(coreboot_node, "ram-code", ram_code()); + + struct coreboot_devicetree_nodes { + int cbmem_id; + const char *dt_node; + const char *dt_compatible; + } sections_ids[] = { + {CBMEM_ID_TIMESTAMP, "coreboot-timestamps", "coreboot-timestamps"}, + {CBMEM_ID_CONSOLE, "coreboot-console", "coreboot-console"}, + {CBMEM_ID_ACPI_GNVS, "coreboot-acpi-gnvs", "coreboot-acpi-gnvs"}, + {CBMEM_ID_ACPI_CNVS, "coreboot-acpi-cnvs", "coreboot-acpi-cnvs"}, + {CBMEM_ID_VPD, "coreboot-vpd", "coreboot-vpd"}, + {CBMEM_ID_WIFI_CALIBRATION, "coreboot-wifi-calibration", "coreboot-wifi-calibration"}, + {CBMEM_ID_TCPA_LOG, "coreboot-tcpa-log", "coreboot-tcpa-log"}, + {CBMEM_ID_FMAP, "coreboot-fmap", "coreboot-fmap"}, + {CBMEM_ID_VBOOT_WORKBUF, "coreboot-vboot-workbuf", "coreboot-vboot-workbuf"}, + {CBMEM_ID_TYPE_C_INFO, "coreboot-type-c-info", "coreboot-type-c-info"}, +}; + + for (int i = 0; i < ARRAY_SIZE(sections_ids); i++) { + const struct cbmem_entry *cbmem_entry = cbmem_entry_find(sections_ids[i].cbmem_id); + if (!cbmem_entry) + continue; // This section is not present + uint64_t section_base = (uintptr_t)cbmem_entry_start(cbmem_entry); + uint64_t section_size = cbmem_entry_size(cbmem_entry); + + const char *node_path[] = { sections_ids[i].dt_node, NULL}; + struct device_tree_node *dt_node = dt_find_node(firmware_node, + node_path, + &addr_cells, &size_cells, 1); + dt_add_string_prop(dt_node, "compatible", sections_ids[i].dt_compatible); + dt_add_reg_prop(dt_node, &section_base, &section_size, 1, addr_cells, size_cells); + } } /* diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index e45ac9f..fc8ae67 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -182,7 +182,10 @@ /* Now that we have collected all of our information * write our configuration tables. */ - write_tables(); + if (CONFIG(COREBOOT_TABLES)) + write_tables(); + else if (CONFIG(FDT_PAYLOAD_HANDOFF)) + write_fdt_handoff(); timestamp_add_now(TS_FINALIZE_CHIPS); dev_finalize_chips(); diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 533411f..6d44223 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -33,7 +33,7 @@ } if ((all_zero < 2) && (all_one < 2)) { - printk(BIOS_DEBUG, "%p:", memory + i); + printk(BIOS_DEBUG, "%04lx:", i); for (j = 0; j < num_bytes; j++) printk(BIOS_DEBUG, " %02x", line[j]); for (; j < 16; j++) diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 637ad13..0b6bcf6 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -251,7 +251,10 @@ printk(BIOS_SPEW, "Loaded segments\n"); /* Pass cbtables to payload if architecture desires it. */ - prog_set_entry(payload, (void *)entry, cbmem_find(CBMEM_ID_CBTABLE)); + if (CONFIG(COREBOOT_TABLES)) + prog_set_entry(payload, (void *)entry, cbmem_find(CBMEM_ID_CBTABLE)); + else if (CONFIG(FDT_PAYLOAD_HANDOFF)) + prog_set_entry(payload, (void *)entry, cbmem_find(CBMEM_ID_FDT_HANDOFF)); return true; } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index a20092f..5f1e1b5 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -17,6 +17,10 @@ select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED + select FDT_PAYLOAD_HANDOFF + +config COREBOOT_TABLES + default n config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 594b256..548ff7f 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -1,5 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <endian.h> +#include <lib.h> +#include <cbfs.h> +#include <fit.h> +#include <bootstate.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/68719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96d4e7805855d35392e78f8d7b3a1ff911105a3 Gerrit-Change-Number: 68719 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: payloads/edk2: Set the correct serial settings for AMD SOCs
by Arthur Heymans (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Sean Rhodes, Martin L Roth, Matt DeVillier, Stefan Reinauer. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68596 ) Change subject: payloads/edk2: Set the correct serial settings for AMD SOCs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > because you don't get serial output on Picasso (and forward) without it I'm confused. This looks like a bug in EDK2. It should parse the coreboot tables and set that PCD at runtime based on that information. -- To view, visit https://review.coreboot.org/c/coreboot/+/68596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70630d21bbdb21f2aa8cbaeb3e842629b97af3ba Gerrit-Change-Number: 68596 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Oct 2022 16:52:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Docs/releases: Update release checklist document
by Angel Pons (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Felix Singer, Jason Glenesk, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68500 ) Change subject: Docs/releases: Update release checklist document ...................................................................... Patch Set 1: (3 comments) File Documentation/releases/checklist.md: https://review.coreboot.org/c/coreboot/+/68500/comment/998a9a30_ab194361 PS1, Line 29: > That seems very nitpicky. Personally I don't think it matters much. […] Ack, we'll change it later if we get annoyed enough. https://review.coreboot.org/c/coreboot/+/68500/comment/4e60aa30_d9715784 PS1, Line 12: Our releases aren't primarily a vehicle for code that is stable across : all boards: The logistics of testing the more than 100 boards that are : spread out all continents (except Antarctica, probably) on a given tree : state are prohibitive for project of our size. : : Instead, the releases are regular breakpoints that serve multiple : purposes: They support cooperation between multiple groups (corporations : or otherwise) in that it's easier to keep source trees synchronized : based on a limited set of commits. They allow a quick assessment of the : age of any given build or source tree based on its git version (4.8-1234 : was merged into master a few months after 4.8, which came out in April : of 2018. 4.0-21718's age is harder to guess). : : And finally we use releases to as points in time where we remove old : code: Once we decide that a certain part of coreboot gets in the way of : future development, we announce on the next release that we intend to : remove that part - and everything that depends on it - after the : following release. So removing feature FOO will be announced in release : X for release X+1. The first commit after X+1 is fair game for such : removal. > I reflowed a bunch of sections because they weren't under 72 characters. Ack, just noted this as there were no changes in the content. https://review.coreboot.org/c/coreboot/+/68500/comment/600460fc_cbf5a6c0 PS1, Line 73: - [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of : boards supported by vboot. > Sorry, what do you mean "when doing the release"? Everything in this list is done as part part of doing the release. > > Do you mean closer to the day of the release? Yes, sorry for the confusion. -- To view, visit https://review.coreboot.org/c/coreboot/+/68500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a79cf92620755e19266faaf593dc2657acdb16f Gerrit-Change-Number: 68500 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Oct 2022 16:24:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Add STB Spill-to-DRAM enum
by 9elements QA (Code Review) 23 Oct '22

23 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68686 ) Change subject: soc/amd/mendocino: Add STB Spill-to-DRAM enum ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 3 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130413 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130412 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130411 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130410 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130409 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130408 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130407 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130406 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130405 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130404 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130403 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130402 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130401 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130400 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130399 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130398 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 Gerrit-Change-Number: 68686 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Oct 2022 16:22:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Kopeć. Hello Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68712 to look at the new patch set (#2). Change subject: mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily ...................................................................... mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily Alder Lake FSP has bugged GPIO definitions for DEVSLP pins 6 and 7 which would cause incorrect programming of those pins when GpioOverride is disabled. Debug FSP will simply assert on DEVSLP programming. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I8b809851cefa339d172b95803aa8f49b441eddba --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 34 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/68712/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b809851cefa339d172b95803aa8f49b441eddba Gerrit-Change-Number: 68712 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mainboard/msi/ms7d25: Configure NCT6687D pin for PECI
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Kopeć. Hello Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68711 to look at the new patch set (#2). Change subject: mainboard/msi/ms7d25: Configure NCT6687D pin for PECI ...................................................................... mainboard/msi/ms7d25: Configure NCT6687D pin for PECI One register configuring multi-pin functions was outside of the Global Configuration Registers space and skipped in the initial port patches. Replicate the vendor configuration and set the Super I/O pin for PECI functionality. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b --- M src/mainboard/msi/ms7d25/bootblock.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/68711/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b Gerrit-Change-Number: 68711 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Felix Held. Hello Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68710 to look at the new patch set (#2). Change subject: util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo ...................................................................... util/superiotool/nuvoton.c: fix NVT6687D PP LDN typo Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the patch adding register definitions for NCT6687D Super I/O chip. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca --- M util/superiotool/nuvoton.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/68710/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca Gerrit-Change-Number: 68710 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily
by Michał Żygowski (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68712 ) Change subject: mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily ...................................................................... mainboard/msi/ms7d25/devicetree.cb: Disable SATA DEVSLP temporarily Alder Lake FSP has bugged GPIO definitions for DEVSLP pins 6 and 7 which would cause incorrect programming of those pins when GpioOverride is disabled. Debug FSP will simply assert on DEVSLP programming. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I8b809851cefa339d172b95803aa8f49b441eddba --- M src/mainboard/msi/ms7d25/devicetree.cb 1 file changed, 34 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/68712/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 189faf6..4485db7 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -14,19 +14,19 @@ # USB Configuration register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # USB-C LAN_USB1 - register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # MSI MYSTIC LIGHT - register "usb2_ports[2]" = "USB2_PORT_MAX(OC0)" # USB-A LAN_USB1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # JUSB5 - register "usb2_ports[4]" = "USB2_PORT_MAX(OC3)" # HUB to rear USB 2.0 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 - register "usb2_ports[10]" = "USB2_PORT_MAX(OC0)" # PS2_USB1 - register "usb2_ports[11]" = "USB2_PORT_MAX(OC0)" # PS2_USB1 - register "usb2_ports[12]" = "USB2_PORT_MAX(OC0)" # HUB to USB 2.0 headers - register "usb2_ports[13]" = "USB2_PORT_MAX(OC6)" # CNVi BT + register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers + register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 @@ -58,16 +58,18 @@ [7] = 1, }" - register "sata_ports_dev_slp" = "{ - [0] = 0, - [1] = 0, - [2] = 0, - [3] = 0, - [4] = 0, - [5] = 0, - [6] = 1, - [7] = 1, - }" + #FIXME: FSP has bugged definitions for DEVSLP pins 6 and 7. + #Enable the pins back when it is fixed or GpioOverride can be enabled. + #register "sata_ports_dev_slp" = "{ + # [0] = 0, + # [1] = 0, + # [2] = 0, + # [3] = 0, + # [4] = 0, + # [5] = 0, + # [6] = 1, + # [7] = 1, + #}" # HDMI on port B register "ddi_portB_config" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/68712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b809851cefa339d172b95803aa8f49b441eddba Gerrit-Change-Number: 68712 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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