coreboot-gerrit October 2022

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[S] Change in coreboot[master]: util/ifdtool: Add Wellsburg support
by build bot (Jenkins) (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Stefan Reinauer, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68657 ) Change subject: util/ifdtool: Add Wellsburg support ...................................................................... Patch Set 4: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161213): https://review.coreboot.org/c/coreboot/+/68657/comment/d1ae24d8_f70ecfb1 PS4, Line 28: Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Non-standard signature: Co-developed-by: -- To view, visit https://review.coreboot.org/c/coreboot/+/68657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Gerrit-Change-Number: 68657 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 06:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ifdtool: Determine max regions from IFD
by Patrick Rudolph (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Stefan Reinauer. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68780 ) Change subject: ifdtool: Determine max regions from IFD ...................................................................... ifdtool: Determine max regions from IFD IFDv1 always has 8 regions, while IFDv2 always has 16 regions. It's platform specific which regions are used or are reserved. The 'SPI programming guide' as the name says is a guide only, not a specification what the hardware actually does. The best to do is not to rely on the guide, but detect how many regions are present in the IFD and expose them all. Very early IFDv2 chipsets, sometimes in-officially referred to as IFDv1.5 platforms, only have 8 regions. To not corrupt the IFD when operating on an IFDv1.5 detect how much space is actually present in the IFD. Fixes IFD corruption on Wellsburg/Lynxpoint when writing a new flash layout. Change-Id: I0e3f23ec580b8b8402eb1bf165e3995c8db633f1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 78 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/68780/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index e97efcc..6cac179 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -296,14 +296,18 @@ static void check_ifd_version(char *image, int size) { + const fdbar_t *fdb = find_fd(image, size); + if (is_platform_ifd_2()) { ifd_version = IFD_VERSION_2; chipset = ifd2_platform_to_chipset(platform); - max_regions = MAX_REGIONS; + max_regions = (max_regions_from_fdbar(fdb) < MAX_REGIONS) ? + max_regions_from_fdbar(fdb) : MAX_REGIONS; } else { ifd_version = IFD_VERSION_1; chipset = ifd1_guess_chipset(image, size); - max_regions = MAX_REGIONS_OLD; + max_regions = (max_regions_from_fdbar(fdb) < MAX_REGIONS_OLD) ? + max_regions_from_fdbar(fdb) : MAX_REGIONS_OLD; } } @@ -410,6 +414,50 @@ region.base, region.limit, region_name_short(num)); } +static int sort_compare(const void *a, const void *b) +{ + return *(size_t *)a - *(size_t *)b; +} + +/* + * IFDv1 always has 8 regions, while IFDv2 always has 16 regions. + * + * It's platform specific which regions are used or are reserved. + * The 'SPI programming guide' as the name says is a guide only, + * not a specification what the hardware actually does. + * The best to do is not to rely on the guide, but detect how many + * regions are present in the IFD and expose them all. + * + * Very early IFDv2 chipsets, sometimes in-officially referred to as + * IFDv1.5 platforms, only have 8 regions. To not corrupt the IFD when + * operating on an IFDv1.5 detect how much space is actually present + * in the IFD. + */ +int max_regions_from_fdbar(const fdbar_t *fdb) +{ + const size_t fcba = (fdb->flmap0 & 0xff) << 4; + const size_t fmba = (fdb->flmap1 & 0xff) << 4; + const size_t frba = ((fdb->flmap0 >> 16) & 0xff) << 4; + const size_t fpsba = ((fdb->flmap1 >> 16) & 0xff) << 4; + const size_t flumap = 4096 - 256 - 4; + size_t sorted[5] = {fcba, fmba, frba, fpsba, flumap}; + + qsort(sorted, ARRAY_SIZE(sorted), sizeof(size_t), sort_compare); + + for (size_t i = 0; i < 4; i++) { + /* + * Find FRBA in the sorted array and determine the size of the + * region by the start of the next region. Every region requires + * 4 bytes of space. + */ + if (sorted[i] == frba) + return ((sorted[i+1] - sorted[i])/4) < MAX_REGIONS ? + ((sorted[i+1] - sorted[i])/4) : MAX_REGIONS; + } + /* Never reaches this point */ + return 0; +} + static void dump_frba(const frba_t *frba) { unsigned int i; diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 1ee76f1..536e56d 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -205,3 +205,5 @@ const char *filename; const char *fmapname; }; + +int max_regions_from_fdbar(const fdbar_t *fdb); \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/68780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e3f23ec580b8b8402eb1bf165e3995c8db633f1 Gerrit-Change-Number: 68780 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: ifdtool: Move regions to seperate file
by Patrick Rudolph (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68695 to look at the new patch set (#5). Change subject: ifdtool: Move regions to seperate file ...................................................................... ifdtool: Move regions to seperate file Change-Id: I6a1ba1799c69881b1f48d903b8f86e7cd93815c2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/ifdtool/Makefile.inc M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h A util/ifdtool/regions.c 4 files changed, 214 insertions(+), 182 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/68695/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a1ba1799c69881b1f48d903b8f86e7cd93815c2 Gerrit-Change-Number: 68695 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/ifdtool: Add Wellsburg support
by Patrick Rudolph (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Stefan Reinauer, Angel Pons. Hello build bot (Jenkins), Stefan Reinauer, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68657 to look at the new patch set (#4). Change subject: util/ifdtool: Add Wellsburg support ...................................................................... util/ifdtool: Add Wellsburg support Wellsburg is IFDv2 compatible, but only has 8 regions and thus has an "IFDv1.5" descriptor. The 'SPI programming guide' is inconsistent and mentions 6 regions in one place, but 7 regions in another chapter. Tests showed that it actually supports 7 regions. Add support using the -p argument to specify Wellsburg platform. The previous patch made sure that only 8 regions are used and that no corruption can happen when operating in IFDv2 mode. Tested on Intel Grangeville. Documents used: Intel Document Id: 516552 Intel Document Id: 565117 Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Co-developed-by: Julian Elischer <jrelis(a)google.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/68657/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Gerrit-Change-Number: 68657 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify PL2 setting to 25w
by Vidya Gopalakrishnan (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Reka Norman, Vidya Gopalakrishnan, Tyler Wang, Peter Ou. Vidya Gopalakrishnan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68523 ) Change subject: mb/google/nissa/var/craask: Modify PL2 setting to 25w ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/craask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68523/comment/cb6c8dc2_75b3f592 PS3, Line 158: }" > Hi Vidya, […] Hi Peter, We need to add pl4 in the original struct and update the value. Responded in the bug as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/68523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 Gerrit-Change-Number: 68523 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 06:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Comment-In-Reply-To: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Yidi Lin (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 05:38:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/geralt: Configure firmware display for eDP panel
by Rex-BC Chen (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68490 ) Change subject: mb/google/geralt: Configure firmware display for eDP panel ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: @yuping, this patch also needs your +2. Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/68490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Gerrit-Change-Number: 68490 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Oct 2022 05:11:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Rex-BC Chen (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Angel Pons, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68659/comment/e1c9d002_7bd53c40 PS4, Line 13: > This adds XXms to boot time. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 05:10:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/systemagent.c: Fix memory type reporting
by Werner Zeh (Code Review) 25 Oct '22

25 Oct '22

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68405 ) Change subject: soc/intel/systemagent.c: Fix memory type reporting ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: This patch introduces a regression. If my tree contains this patch, the boot dies with the following last debug message: [DEBUG] apm_control: Finalizing SMM. Having a look with a HW debugger shows that the CPU has crashed completely. I am able to reproduce this issue on Elkhart Lake (mc_ehl2). Looks like Apollo Lake is affected, too (have not tesed myself). If I revert this and the following patch on top of master, everything is fine again. -- To view, visit https://review.coreboot.org/c/coreboot/+/68405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Gerrit-Change-Number: 68405 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 05:10:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Rex-BC Chen (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Bayi Cheng, Angel Pons, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68659 to look at the new patch set (#5). Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz According to the datasheet, the maximum frequency supported by W25Q64JWZPIM (Winbond) is 50MHz. To meet this restriction, we lower the NOR clock from 52MHz to 39MHz which is the closest frequency of the next clock level on MT8186. This adds about 15ms to boot time. BUG=b:253167106 TEST=emerge-corsola coreboot. BRANCH=corsola Signed-off-by: Dandan He <dandan.he(a)mediatek.corp-partner.google.com> Signed-off-by: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd --- M src/soc/mediatek/mt8186/pll.c 1 file changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/68659/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022