coreboot-gerrit October 2022

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Derek Huang (Code Review) 25 Oct '22

25 Oct '22

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Raymond Chung (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Derek Huang, Tim Wawrzynczak, Zhuohao Lee. Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68806 ) Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/gaelin/memory.c: https://review.coreboot.org/c/coreboot/+/68806/comment/e37e058b_ac5411d6 PS3, Line 33: bool variant_is_half_populated(void) : { : return false; : } : > The function is not needed. It is in baseboard/brask/memory. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 5 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 04:33:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Raymond Chung (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Derek Huang, Tim Wawrzynczak, Zhuohao Lee. Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68806 ) Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68806/comment/d8b1e0ca_a6ca11e9 PS3, Line 14: brask > firmware-brya-14505. […] Done https://review.coreboot.org/c/coreboot/+/68806/comment/5577aa7a_207dba08 PS3, Line 15: emerge-brask coreboot > Build and pass MRC memory training Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 5 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 04:33:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Raymond Chung (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Raymond Chung, Tim Wawrzynczak, Zhuohao Lee. Hello build bot (Jenkins), Derek Huang, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68806 to look at the new patch set (#4). Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and pass MRC memory training Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> --- A src/mainboard/google/brya/variants/gaelin/Makefile.inc A src/mainboard/google/brya/variants/gaelin/memory.c 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/68806/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 4 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Attention: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Derek Huang (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Raymond Chung, Tim Wawrzynczak, Zhuohao Lee. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68806 ) Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68806/comment/fee6d1d8_d2124cc1 PS3, Line 14: brask firmware-brya-14505.B https://review.coreboot.org/c/coreboot/+/68806/comment/07900394_21450c47 PS3, Line 15: emerge-brask coreboot Build and pass MRC memory training File src/mainboard/google/brya/variants/gaelin/memory.c: https://review.coreboot.org/c/coreboot/+/68806/comment/d8e46672_489d8599 PS3, Line 33: bool variant_is_half_populated(void) : { : return false; : } : The function is not needed. It is in baseboard/brask/memory.c already, you are doing the same here so you don't need to override it. -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 3 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-Attention: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 03:35:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Raymond Chung (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Derek Huang, Tim Wawrzynczak, Zhuohao Lee. Hello Derek Huang, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68806 to look at the new patch set (#3). Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:249000573 BRANCH=brask TEST=emerge-brask coreboot Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> --- A src/mainboard/google/brya/variants/gaelin/Makefile.inc A src/mainboard/google/brya/variants/gaelin/memory.c 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/68806/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 3 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Raymond Chung (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Derek Huang, Tim Wawrzynczak, Zhuohao Lee. Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68806 ) Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68806/comment/7dbd5da0_15bb62e9 PS1, Line 9: The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 2 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 03:16:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
by EricKY Cheng (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Tim Van Patten, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68469 ) Change subject: soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/mendocino/chip.h: https://review.coreboot.org/c/coreboot/+/68469/comment/5fead937_9162b7ed PS4, Line 77: uint32_t sustained_power_limit_mW_B; : uint32_t fast_ppt_limit_mW_B; : uint32_t slow_ppt_limit_mW_B; : uint32_t slow_ppt_time_constant_s_B; : uint32_t thermctl_limit_degreeC_B; > Let's reduce the change to only what's necessary, meaning only the settings that are actually changi […] Hi Tim, As thermal's feedback b/248086651#comment14, those settings are needed. Please help to reply thermal team on b/248086651 and I can follow your final design to modify changes. BR, Eric KY Cheng -- To view, visit https://review.coreboot.org/c/coreboot/+/68469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd Gerrit-Change-Number: 68469 Gerrit-PatchSet: 8 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 03:15:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by Raymond Chung (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68806 to look at the new patch set (#2). Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:249000573 BRANCH=brask Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> --- A src/mainboard/google/brya/variants/gaelin/Makefile.inc A src/mainboard/google/brya/variants/gaelin/memory.c 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/68806/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 2 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
by build bot (Jenkins) (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68806 ) Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161210): https://review.coreboot.org/c/coreboot/+/68806/comment/5aa29211_bcf9a8c1 PS1, Line 9: The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Gerrit-Change-Number: 68806 Gerrit-PatchSet: 1 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 03:11:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022