coreboot-gerrit October 2022

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[M] Change in coreboot[master]: soc/mediatek: Add support for input 1P mode of dp_intf
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68485 ) Change subject: soc/mediatek: Add support for input 1P mode of dp_intf ...................................................................... soc/mediatek: Add support for input 1P mode of dp_intf MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct member `input_mode` is added to `struct mtk_dpintf` for differentiation. We also move SoC-specific data `dpintf_data` to soc folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/common/dp/dp_intf.c M src/soc/mediatek/common/dp/include/soc/dp_intf.h M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/dp_intf.c 4 files changed, 69 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/dp/dp_intf.c b/src/soc/mediatek/common/dp/dp_intf.c index ab2070e..ca531b5 100644 --- a/src/soc/mediatek/common/dp/dp_intf.c +++ b/src/soc/mediatek/common/dp/dp_intf.c @@ -9,22 +9,22 @@ #include <soc/pll_common.h> #include <soc/spm.h> -static void mtk_dpintf_mask(struct mtk_dpintf *dpintf, u32 offset, u32 val, u32 mask) +static void mtk_dpintf_mask(const struct mtk_dpintf *dpintf, u32 offset, u32 val, u32 mask) { clrsetbits32(dpintf->regs + offset, mask, val); } -static void mtk_dpintf_sw_reset(struct mtk_dpintf *dpintf, bool reset) +static void mtk_dpintf_sw_reset(const struct mtk_dpintf *dpintf, bool reset) { mtk_dpintf_mask(dpintf, DPINTF_RET, reset ? RST : 0, RST); } -static void mtk_dpintf_enable(struct mtk_dpintf *dpintf) +static void mtk_dpintf_enable(const struct mtk_dpintf *dpintf) { mtk_dpintf_mask(dpintf, DPINTF_EN, EN, EN); } -static void mtk_dpintf_config_hsync(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_hsync(const struct mtk_dpintf *dpintf, struct mtk_dpintf_sync_param *sync) { mtk_dpintf_mask(dpintf, DPINTF_TGEN_HWIDTH, @@ -35,7 +35,7 @@ sync->front_porch << HFP, HFP_MASK); } -static void mtk_dpintf_config_vsync(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_vsync(const struct mtk_dpintf *dpintf, struct mtk_dpintf_sync_param *sync, u32 width_addr, u32 porch_addr) { @@ -53,35 +53,35 @@ VSYNC_FRONT_PORCH_MASK); } -static void mtk_dpintf_config_vsync_lodd(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_vsync_lodd(const struct mtk_dpintf *dpintf, struct mtk_dpintf_sync_param *sync) { mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH, DPINTF_TGEN_VPORCH); } -static void mtk_dpintf_config_vsync_leven(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_vsync_leven(const struct mtk_dpintf *dpintf, struct mtk_dpintf_sync_param *sync) { mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_LEVEN, DPINTF_TGEN_VPORCH_LEVEN); } -static void mtk_dpintf_config_vsync_rodd(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_vsync_rodd(const struct mtk_dpintf *dpintf, struct mtk_dpintf_sync_param *sync) { mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_RODD, DPINTF_TGEN_VPORCH_RODD); } -static void mtk_dpintf_config_vsync_reven(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_vsync_reven(const struct mtk_dpintf *dpintf, struct mtk_dpintf_sync_param *sync) { mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_REVEN, DPINTF_TGEN_VPORCH_REVEN); } -static void mtk_dpintf_config_pol(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_pol(const struct mtk_dpintf *dpintf, struct mtk_dpintf_polarities *dpintf_pol) { u32 pol; @@ -91,24 +91,24 @@ mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, pol, HSYNC_POL | VSYNC_POL); } -static void mtk_dpintf_config_3d(struct mtk_dpintf *dpintf, bool en_3d) +static void mtk_dpintf_config_3d(const struct mtk_dpintf *dpintf, bool en_3d) { mtk_dpintf_mask(dpintf, DPINTF_CON, en_3d ? TDFP_EN : 0, TDFP_EN); } -static void mtk_dpintf_config_interface(struct mtk_dpintf *dpintf, bool inter) +static void mtk_dpintf_config_interface(const struct mtk_dpintf *dpintf, bool inter) { mtk_dpintf_mask(dpintf, DPINTF_CON, inter ? INTL_EN : 0, INTL_EN); } -static void mtk_dpintf_config_fb_size(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_fb_size(const struct mtk_dpintf *dpintf, u32 width, u32 height) { mtk_dpintf_mask(dpintf, DPINTF_SIZE, width << HSIZE, HSIZE_MASK); mtk_dpintf_mask(dpintf, DPINTF_SIZE, height << VSIZE, VSIZE_MASK); } -static void mtk_dpintf_config_channel_limit(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_channel_limit(const struct mtk_dpintf *dpintf, struct mtk_dpintf_yc_limit *limit) { mtk_dpintf_mask(dpintf, DPINTF_Y_LIMIT, @@ -121,7 +121,7 @@ limit->c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK); } -static void mtk_dpintf_config_bit_num(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_bit_num(const struct mtk_dpintf *dpintf, enum mtk_dpintf_out_bit_num num) { u32 val; @@ -146,7 +146,7 @@ mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, OUT_BIT_MASK); } -static void mtk_dpintf_config_channel_swap(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_channel_swap(const struct mtk_dpintf *dpintf, enum mtk_dpintf_out_channel_swap swap) { u32 val; @@ -178,12 +178,12 @@ mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, CH_SWAP_MASK); } -static void mtk_dpintf_config_yuv422_enable(struct mtk_dpintf *dpintf, bool enable) +static void mtk_dpintf_config_yuv422_enable(const struct mtk_dpintf *dpintf, bool enable) { mtk_dpintf_mask(dpintf, DPINTF_CON, enable ? YUV422_EN : 0, YUV422_EN); } -static void mtk_dpintf_config_color_format(struct mtk_dpintf *dpintf, +static void mtk_dpintf_config_color_format(const struct mtk_dpintf *dpintf, enum mtk_dpintf_out_color_format format) { bool enable; @@ -206,7 +206,7 @@ mtk_dpintf_config_channel_swap(dpintf, channel_swap); } -static int mtk_dpintf_power_on(struct mtk_dpintf *dpintf, const struct edid *edid) +static int mtk_dpintf_power_on(const struct mtk_dpintf *dpintf, const struct edid *edid) { u32 clksrc; u32 pll_rate; @@ -228,7 +228,7 @@ return 0; } -static int mtk_dpintf_set_display_mode(struct mtk_dpintf *dpintf, +static int mtk_dpintf_set_display_mode(const struct mtk_dpintf *dpintf, const struct edid *edid) { struct mtk_dpintf_yc_limit limit; @@ -284,7 +284,7 @@ mtk_dpintf_config_channel_swap(dpintf, dpintf->channel_swap); mtk_dpintf_config_color_format(dpintf, dpintf->color_format); - mtk_dpintf_mask(dpintf, DPINTF_CON, INPUT_2P_EN, INPUT_2P_EN); + mtk_dpintf_mask(dpintf, DPINTF_CON, dpintf->input_mode, INPUT_2P_EN); mtk_dpintf_sw_reset(dpintf, false); return 0; @@ -292,14 +292,8 @@ void dp_intf_config(const struct edid *edid) { - struct mtk_dpintf dpintf = { - .regs = (void *)(DP_INTF0_BASE), - .color_format = MTK_DPINTF_COLOR_FORMAT_RGB, - .yc_map = MTK_DPINTF_OUT_YC_MAP_RGB, - .bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS, - .channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB, - }; + const struct mtk_dpintf *data = &dpintf_data; - mtk_dpintf_power_on(&dpintf, edid); - mtk_dpintf_set_display_mode(&dpintf, edid); + mtk_dpintf_power_on(data, edid); + mtk_dpintf_set_display_mode(data, edid); } diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf.h b/src/soc/mediatek/common/dp/include/soc/dp_intf.h index bb04716..240a7e2 100644 --- a/src/soc/mediatek/common/dp/include/soc/dp_intf.h +++ b/src/soc/mediatek/common/dp/include/soc/dp_intf.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_COMMON_DP_DP_INTF_H #include <edid.h> +#include <types.h> #define DPINTF_EN 0x00 #define EN BIT(0) @@ -211,6 +212,11 @@ MTK_DPINTF_COLOR_FORMAT_YCBCR_422_FULL, }; +enum mtk_dpintf_input_mode { + MTK_DPINTF_INPUT_MODE_1P = 0, + MTK_DPINTF_INPUT_MODE_2P = INPUT_2P_EN, +}; + enum TVDPLL_CLK { TVDPLL_PLL = 0, TVDPLL_D2 = 1, @@ -225,6 +231,7 @@ enum mtk_dpintf_out_yc_map yc_map; enum mtk_dpintf_out_bit_num bit_num; enum mtk_dpintf_out_channel_swap channel_swap; + enum mtk_dpintf_input_mode input_mode; }; enum mtk_dpintf_polarity { @@ -253,6 +260,8 @@ u16 c_bottom; }; +extern const struct mtk_dpintf dpintf_data; + void dp_intf_config(const struct edid *edid); #endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_H */ diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index f8b3510..84cd802 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -46,7 +46,7 @@ ramstage-y += ../common/dfd.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c -ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c +ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += emi.c ramstage-y += hdmi.c ramstage-y += ../common/mcu.c diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c new file mode 100644 index 0000000..9c0cea6 --- /dev/null +++ b/src/soc/mediatek/mt8195/dp_intf.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <soc/dp_intf.h> + +const struct mtk_dpintf dpintf_data = { + .regs = (void *)(DP_INTF0_BASE), + .color_format = MTK_DPINTF_COLOR_FORMAT_RGB, + .yc_map = MTK_DPINTF_OUT_YC_MAP_RGB, + .bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS, + .channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB, + .input_mode = MTK_DPINTF_INPUT_MODE_2P, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/68485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba Gerrit-Change-Number: 68485 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/mediatek: Move DP drivers to common
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68484 ) Change subject: soc/mediatek: Move DP drivers to common ...................................................................... soc/mediatek: Move DP drivers to common DP drivers can be shared for both MT8195 and MT8188, so move them to common folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- R src/soc/mediatek/common/dp/dp_intf.c R src/soc/mediatek/common/dp/dptx.c R src/soc/mediatek/common/dp/dptx_hal.c R src/soc/mediatek/common/dp/include/soc/dp_intf.h R src/soc/mediatek/common/dp/include/soc/dptx.h R src/soc/mediatek/common/dp/include/soc/dptx_hal.h R src/soc/mediatek/common/dp/include/soc/dptx_reg.h M src/soc/mediatek/mt8195/Makefile.inc 8 files changed, 34 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/common/dp/dp_intf.c similarity index 100% rename from src/soc/mediatek/mt8195/dp_intf.c rename to src/soc/mediatek/common/dp/dp_intf.c diff --git a/src/soc/mediatek/mt8195/dptx.c b/src/soc/mediatek/common/dp/dptx.c similarity index 100% rename from src/soc/mediatek/mt8195/dptx.c rename to src/soc/mediatek/common/dp/dptx.c diff --git a/src/soc/mediatek/mt8195/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c similarity index 100% rename from src/soc/mediatek/mt8195/dptx_hal.c rename to src/soc/mediatek/common/dp/dptx_hal.c diff --git a/src/soc/mediatek/mt8195/include/soc/dp_intf.h b/src/soc/mediatek/common/dp/include/soc/dp_intf.h similarity index 97% rename from src/soc/mediatek/mt8195/include/soc/dp_intf.h rename to src/soc/mediatek/common/dp/include/soc/dp_intf.h index ee142bf..bb04716 100644 --- a/src/soc/mediatek/mt8195/include/soc/dp_intf.h +++ b/src/soc/mediatek/common/dp/include/soc/dp_intf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_MT8195_DP_INTF_H -#define SOC_MEDIATEK_MT8195_DP_INTF_H +#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_H +#define SOC_MEDIATEK_COMMON_DP_DP_INTF_H #include <edid.h> @@ -255,4 +255,4 @@ void dp_intf_config(const struct edid *edid); -#endif /* SOC_MEDIATEK_MT8195_DP_INTF_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx.h b/src/soc/mediatek/common/dp/include/soc/dptx.h similarity index 91% rename from src/soc/mediatek/mt8195/include/soc/dptx.h rename to src/soc/mediatek/common/dp/include/soc/dptx.h index 54b28ec..b473301 100644 --- a/src/soc/mediatek/mt8195/include/soc/dptx.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_MT8195_DPTX_H -#define SOC_MEDIATEK_MT8195_DPTX_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_H #define DPTX_TBC_BUF_READSTARTADRTHRD 0x08 #define ENABLE_DPTX_EF_MODE 0x1 @@ -74,4 +74,4 @@ int mtk_edp_init(struct edid *edid); -#endif /* SOC_MEDIATEK_MT8195_DPTX_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal.h similarity index 96% rename from src/soc/mediatek/mt8195/include/soc/dptx_hal.h rename to src/soc/mediatek/common/dp/include/soc/dptx_hal.h index dcb1717..d430b6a 100644 --- a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_MT8195_DPTX_HAL_H -#define SOC_MEDIATEK_MT8195_DPTX_HAL_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H #define AUX_CMD_I2C_R_MOT0 0x1 #define AUX_CMD_I2C_R 0x5 @@ -100,4 +100,4 @@ void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value); void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable); -#endif /* SOC_MEDIATEK_MT8195_DPTX_HAL_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_reg.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg.h similarity index 99% rename from src/soc/mediatek/mt8195/include/soc/dptx_reg.h rename to src/soc/mediatek/common/dp/include/soc/dptx_reg.h index a010517..a385eb8 100644 --- a/src/soc/mediatek/mt8195/include/soc/dptx_reg.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_MT8195_DRTX_REG_H -#define SOC_MEDIATEK_MT8195_DRTX_REG_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_REG_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_REG_H #define TOP_OFFSET 0x2000 #define ENC0_OFFSET 0x3000 @@ -4737,4 +4737,4 @@ #define DPCD_69494 0x69494 #define DPCD_69518 0x69518 -#endif /* SOC_MEDIATEK_MT8195_DRTX_REG_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_REG_H */ diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 2d50506..f8b3510 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -46,7 +46,7 @@ ramstage-y += ../common/dfd.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c -ramstage-y += dp_intf.c dptx.c dptx_hal.c +ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c ramstage-y += emi.c ramstage-y += hdmi.c ramstage-y += ../common/mcu.c @@ -66,6 +66,7 @@ ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/include -- To view, visit https://review.coreboot.org/c/coreboot/+/68484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4 Gerrit-Change-Number: 68484 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/geralt: Configure firmware display for eDP panel
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68490 ) Change subject: mb/google/geralt: Configure firmware display for eDP panel ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Gerrit-Change-Number: 68490 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Oct 2022 08:25:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: MAINTAINERS: Update instructions
by Elyes Haouas (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Martin L Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68705 ) Change subject: MAINTAINERS: Update instructions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e06ac5f92109757143897f3d331aeea0cefe4b9 Gerrit-Change-Number: 68705 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 08:25:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/systemagent.c: Fix memory type reporting
by Jan Samek (Code Review) 25 Oct '22

25 Oct '22

Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68405 ) Change subject: soc/intel/systemagent.c: Fix memory type reporting ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > This patch introduces a regression. […] From my testing on mc_apl2, based upon 193e86b814, APL doesn't seem to be affected by this. -- To view, visit https://review.coreboot.org/c/coreboot/+/68405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Gerrit-Change-Number: 68405 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 08:06:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945: Check if channel 0 and 1 are populated
by build bot (Jenkins) (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68781 ) Change subject: nb/intel/i945: Check if channel 0 and 1 are populated ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161222): https://review.coreboot.org/c/coreboot/+/68781/comment/be8b8c2c_d84021fc PS1, Line 10: to true only if channel 0 and 1 are populated. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia77861e5f44501b5d92707977597e143b439e9d4 Gerrit-Change-Number: 68781 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 25 Oct 2022 08:00:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945: Check if channel 0 and 1 are populated
by Elyes Haouas (Code Review) 25 Oct '22

25 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68781 ) Change subject: nb/intel/i945: Check if channel 0 and 1 are populated ...................................................................... nb/intel/i945: Check if channel 0 and 1 are populated Even if the system support dual operation, set 'sysinfo->dual_channel' to true only if channel 0 and 1 are populated. Use 'sysinfo->dual_channel' for 'sdram_rcomp_buffer_strength_and_slew()'. Change-Id: Ia77861e5f44501b5d92707977597e143b439e9d4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 24 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/68781/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 2613b81..86bd689 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -293,6 +293,8 @@ int i, j; u8 raw_spd[SPD_SIZE_MAX_DDR2]; u8 dimm_mask = 0; + bool channel0_populated = false; + bool channel1_populated = false; memset(saved_timings, 0, sizeof(*saved_timings)); saved_timings->max_tRR = UINT32_MAX; @@ -314,10 +316,8 @@ printk(BIOS_DEBUG, "This mainboard supports "); if (sdram_capabilities_dual_channel()) { - sysinfo->dual_channel = true; printk(BIOS_DEBUG, "Dual Channel Operation.\n"); } else { - sysinfo->dual_channel = false; printk(BIOS_DEBUG, "only Single Channel Operation.\n"); } @@ -462,6 +462,12 @@ if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) /* FIXME: Possibly does not boot in this case */ printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); + + if (dimm_mask & ((1 << DIMM_SOCKETS) - 1)) + channel0_populated = true; + if (dimm_mask >> DIMM_SOCKETS & ((1 << DIMM_SOCKETS) - 1)) + channel1_populated = true; + sysinfo->dual_channel = channel0_populated & channel1_populated; } static void choose_tclk(struct sys_info *sysinfo, struct timings *saved_timings) @@ -904,20 +910,18 @@ { const u8 *strength_multiplier; int idx; - bool dual_channel; + bool dual_channel = sysinfo->dual_channel; /* Set Strength Multipliers */ /* Dual Channel needs different tables. */ - if (sdram_capabilities_dual_channel()) { + if (dual_channel) { printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; - dual_channel = true; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; - dual_channel = false; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1]; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia77861e5f44501b5d92707977597e143b439e9d4 Gerrit-Change-Number: 68781 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya: Create marasov variant
by Frank Chu (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Nick Vaccaro. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68575 ) Change subject: mb/google/brya: Create marasov variant ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2e30c203ee0dfa6c887a707e9b5074ce89f57ac Gerrit-Change-Number: 68575 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 07:37:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Create marasov variant
by build bot (Jenkins) (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Nick Vaccaro. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68575 ) Change subject: mb/google/brya: Create marasov variant ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161221): https://review.coreboot.org/c/coreboot/+/68575/comment/9b25df4b_bd44f12a PS3, Line 9: # See util/spd_tools/README.md for more details and instructions. 'README' may be misspelled - perhaps 'README'? -- To view, visit https://review.coreboot.org/c/coreboot/+/68575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2e30c203ee0dfa6c887a707e9b5074ce89f57ac Gerrit-Change-Number: 68575 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 07:36:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Create marasov variant
by Frank Chu (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Nick Vaccaro. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68575 to look at the new patch set (#3). Change subject: mb/google/brya: Create marasov variant ...................................................................... mb/google/brya: Create marasov variant Create the marasov variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:254365935 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MARASOV Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Ib2e30c203ee0dfa6c887a707e9b5074ce89f57ac --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/marasov/include/variant/ec.h A src/mainboard/google/brya/variants/marasov/include/variant/gpio.h A src/mainboard/google/brya/variants/marasov/memory/Makefile.inc A src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/marasov/overridetree.cb 8 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/68575/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2e30c203ee0dfa6c887a707e9b5074ce89f57ac Gerrit-Change-Number: 68575 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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