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[M] Change in coreboot[master]: test]: Add intel CPUID F6x support
by Elyes Haouas (Code Review) 25 Oct '22

25 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68782 ) Change subject: test]: Add intel CPUID F6x support ...................................................................... test]: Add intel CPUID F6x support Change-Id: Iaacb856a0064ea57cdcec11a76fab1cd340e2ed8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/intel/Kconfig A src/cpu/intel/model_f6x/Kconfig A src/cpu/intel/model_f6x/Makefile.inc A src/cpu/intel/model_f6x/model_f6x_init.c M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/speedstep/speedstep.c 7 files changed, 121 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/68782/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 43b360b..6fb057e 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -13,6 +13,7 @@ source "src/cpu/intel/model_f2x/Kconfig" source "src/cpu/intel/model_f3x/Kconfig" source "src/cpu/intel/model_f4x/Kconfig" +source "src/cpu/intel/model_f6x/Kconfig" source "src/cpu/intel/haswell/Kconfig" # Sockets/Slots source "src/cpu/intel/slot_1/Kconfig" diff --git a/src/cpu/intel/model_f6x/Kconfig b/src/cpu/intel/model_f6x/Kconfig new file mode 100644 index 0000000..a5b44c9 --- /dev/null +++ b/src/cpu/intel/model_f6x/Kconfig @@ -0,0 +1,5 @@ +config CPU_INTEL_MODEL_F6X + bool + select ARCH_X86 + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc new file mode 100644 index 0000000..1aaed0a --- /dev/null +++ b/src/cpu/intel/model_f6x/Makefile.inc @@ -0,0 +1,5 @@ +ramstage-y += model_f6x_init.c +subdirs-y += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c + +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-06-*) diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c new file mode 100644 index 0000000..85ef9bd --- /dev/null +++ b/src/cpu/intel/model_f6x/model_f6x_init.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <device/device.h> + +static void configure_mca(void) +{ + msr_t msr; + int i; + const unsigned int num_banks = mca_get_bank_count(); + + /* Enable all error reporting */ + msr.lo = msr.hi = ~0; + for (i = 0; i < num_banks; i++) + wrmsr(IA32_MC_CTL(i), msr); + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_clear_status(); +} + + +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 10); /* FERR# multiplexing */ + /* FIXME:SpeedStep Enable - here it hang, but it shouldn't */ + //msr.lo |= (1 << 16); + wrmsr(IA32_MISC_ENABLE, msr); +} + +static void model_f6x_init(struct device *cpu) +{ + + /* Clear out pending MCEs */ + configure_mca(); + + /* Turn on caching if we haven't already */ + enable_cache(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); +}; + +static struct device_operations cpu_dev_ops = { + .init = model_f6x_init, +}; + +static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x0f62 }, /* Not tested */ + { X86_VENDOR_INTEL, 0x0f64 }, /* Not tested */ + { X86_VENDOR_INTEL, 0x0f65 }, + { X86_VENDOR_INTEL, 0x0f68 }, /* Not tested */ + { 0, 0 }, +}; + +static const struct cpu_driver model_f6x __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 3c9f262..c6abd10 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -8,6 +8,7 @@ select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X + select CPU_INTEL_MODEL_F6X select CPU_INTEL_MODEL_1067X select MMX select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 9b08be6..259808d 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -1,6 +1,7 @@ subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x +subdirs-y += ../model_f6x subdirs-y += ../model_1067x subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 9235272..7e8a3de 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -16,23 +16,31 @@ static void speedstep_get_limits(sst_params_t *const params) { msr_t msr; + struct cpuinfo_x86 c; - const uint16_t cpu_id = (cpuid_eax(1) >> 4) & 0xffff; + get_fms(&c, cpuid_eax(1)); const uint32_t state_mask = /* Penryn supports non integer (i.e. half) ratios. */ - ((cpu_id == 0x1067) ? SPEEDSTEP_RATIO_NONINT : 0) + ((c.x86 == 6 && c.x86_model == 0x17) ? + SPEEDSTEP_RATIO_NONINT : 0) | SPEEDSTEP_RATIO_VALUE_MASK | SPEEDSTEP_VID_MASK; + const bool msr_extended_config_supported = c.x86 != 0xf; + const bool msr_platform_info_supported = c.x86 != 0xf; + /* Initialize params to zero. */ memset(params, '\0', sizeof(*params)); + if (msr_extended_config_supported) { /* Read Super-LFM parameters. */ - if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and - enabled bits */ - msr = rdmsr(MSR_FSB_CLOCK_VCC); - params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); - params->slfm.dynfsb = 1; - params->slfm.is_slfm = 1; + /* If (supported and enabled bits) */ + if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) { + msr = rdmsr(MSR_FSB_CLOCK_VCC); + params->slfm = + SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + params->slfm.dynfsb = 1; + params->slfm.is_slfm = 1; + } } /* Read normal minimum parameters. */ @@ -45,7 +53,7 @@ when using turbo mode. */ msr = rdmsr(IA32_PLATFORM_ID); params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); - if (cpu_id == 0x006e) { + if ((c.x86 == 6 && c.x86_model == 0xe) || c.x86 == 0xf) { /* Looks like Yonah CPUs don't have the frequency ratio in IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading should be reliable as those CPUs don't have turbo mode. */ @@ -54,41 +62,38 @@ >> SPEEDSTEP_RATIO_SHIFT; } - /* Read turbo parameters. */ - msr = rdmsr(MSR_FSB_CLOCK_VCC); - if ((msr.hi & (1 << (63 - 32))) && - /* supported and */ - !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { - /* not disabled */ - params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); - params->turbo.is_turbo = 1; + if (msr_platform_info_supported) { + /* Read turbo parameters. */ + msr = rdmsr(MSR_FSB_CLOCK_VCC); + if ((msr.hi & (1 << (63 - 32))) && + /* supported and */ + !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { + /* not disabled */ + params->turbo = + SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); + params->turbo.is_turbo = 1; + } } /* Set power limits by processor type. */ /* Defined values match the normal voltage versions only. But they are only a hint for OSPM, so this should not hurt much. */ - switch (cpu_id) { - case 0x006e: + if (c.x86 == 6 && c.x86_model == 0xe) { /* Yonah */ params->min.power = SPEEDSTEP_MIN_POWER_YONAH; params->max.power = SPEEDSTEP_MAX_POWER_YONAH; - break; - case 0x1067: + } else if (c.x86 == 6 && c.x86_model == 0x17) { /* Penryn */ params->slfm.power = SPEEDSTEP_SLFM_POWER_PENRYN; params->min.power = SPEEDSTEP_MIN_POWER_PENRYN; params->max.power = SPEEDSTEP_MAX_POWER_PENRYN; params->turbo.power = SPEEDSTEP_MAX_POWER_PENRYN; - break; - case 0x006f: - /* Merom */ - default: + } else { /* Use Merom values by default (as before). */ params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM; params->min.power = SPEEDSTEP_MIN_POWER_MEROM; params->max.power = SPEEDSTEP_MAX_POWER_MEROM; params->turbo.power = SPEEDSTEP_MAX_POWER_MEROM; - break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaacb856a0064ea57cdcec11a76fab1cd340e2ed8 Gerrit-Change-Number: 68782 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable DPTC support
by EricKY Cheng (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Jason Nein, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Jason Nein, Martin Roth, Tim Van Patten, Eric Peers, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Moises Garcia, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68076 to look at the new patch set (#5). Change subject: mb/google/skyrim/var/winterhold: Enable DPTC support ...................................................................... mb/google/skyrim/var/winterhold: Enable DPTC support Enable DPTC support for Winterhold BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I97c2d3ee29687cd8a9c459e90a45cef05ac4436b --- M src/mainboard/google/skyrim/Kconfig.name 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/68076/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97c2d3ee29687cd8a9c459e90a45cef05ac4436b Gerrit-Change-Number: 68076 Gerrit-PatchSet: 5 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nein <finaljason(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Jason Nein <finaljason(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS4: > Verified by ODM in b/253167106#comment44. There're still discussions ongoing. -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 08:34:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MIT
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68759 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MIT ...................................................................... soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MIT For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so replace "GPL-2.0-only" with "GPL-2.0-only OR MIT". Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/include/soc/tracker.h 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/include/soc/tracker.h b/src/soc/mediatek/mt8188/include/soc/tracker.h index 6555d70..3534dd5 100644 --- a/src/soc/mediatek/mt8188/include/soc/tracker.h +++ b/src/soc/mediatek/mt8188/include/soc/tracker.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #ifndef SOC_MEDIATEK_MT8188_TRACKER_H #define SOC_MEDIATEK_MT8188_TRACKER_H -- To view, visit https://review.coreboot.org/c/coreboot/+/68759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491 Gerrit-Change-Number: 68759 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Rex-BC Chen, Angel Pons. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68659 ) Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52MHz to 39MHz ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd Gerrit-Change-Number: 68659 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Bayi Cheng <bayi.cheng(a)mediatek.corp-partner.google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 08:31:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/geralt: Configure firmware display for eDP panel
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68490 ) Change subject: mb/google/geralt: Configure firmware display for eDP panel ...................................................................... mb/google/geralt: Configure firmware display for eDP panel Add eDP panel power-on sequences and initialize the display in the ramstage. eDP panel in MT8188 EVB: "IVO R140NWF5 RH". Panel spec name: R140NWF5 RH Product Specification Firmware display eDP panel logs: configure_display: Starting display initialization SINK DPCD version: 0x11 SINK SUPPORT SSC! Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 BUG=b:244208960 TEST=see firmware display using eDP panel in MT8188 EVB. Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/geralt/Kconfig M src/mainboard/google/geralt/Makefile.inc A src/mainboard/google/geralt/display.c A src/mainboard/google/geralt/display.h M src/mainboard/google/geralt/gpio.h M src/mainboard/google/geralt/mainboard.c 6 files changed, 134 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index 11a2d7b..a911cb8 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -28,6 +28,8 @@ select I2C_TPM if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT select TPM_GOOGLE_TI50 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER config MAINBOARD_DIR string diff --git a/src/mainboard/google/geralt/Makefile.inc b/src/mainboard/google/geralt/Makefile.inc index 8da2ecf..85748dd 100644 --- a/src/mainboard/google/geralt/Makefile.inc +++ b/src/mainboard/google/geralt/Makefile.inc @@ -15,6 +15,7 @@ ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c +ramstage-y += display.c ramstage-y += mainboard.c ramstage-y += regulator.c ramstage-y += reset.c diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c new file mode 100644 index 0000000..3db9171 --- /dev/null +++ b/src/mainboard/google/geralt/display.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <edid.h> +#include <framebuffer_info.h> +#include <gpio.h> +#include <soc/ddp.h> +#include <soc/dptx.h> +#include <soc/gpio_common.h> +#include <soc/mtcmos.h> + +#include "display.h" +#include "gpio.h" + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_edp_panel_backlight(void) +{ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_EDP_BL_PWM_1V8, 0); +} + +static void power_on_edp_panel(void) +{ + gpio_output(GPIO_EN_PP3300_EDP_DISP_X, 1); + gpio_set_pull(GPIO_EDP_HPD_1V8, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode(GPIO_EDP_HPD_1V8, 4); +} + +int configure_display(void) +{ + struct edid edid; + struct fb_info *info; + const char *name; + + printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); + + mtcmos_display_power_on(); + configure_edp_panel_backlight(); + power_on_edp_panel(); + + mtk_ddp_init(); + mdelay(200); + + if (mtk_edp_init(&edid) < 0) { + printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); + return -1; + } + name = edid.ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, + edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, + edid.mode.refresh); + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_mode_set(&edid); + info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); + if (info) + fb_set_orientation(info, LB_FB_ORIENTATION_NORMAL); + + return 0; +} diff --git a/src/mainboard/google/geralt/display.h b/src/mainboard/google/geralt/display.h new file mode 100644 index 0000000..29153b3 --- /dev/null +++ b/src/mainboard/google/geralt/display.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_GERALT_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_GERALT_DISPLAY_H__ + +int configure_display(void); + +#endif diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/gpio.h index 5be09ce..df2520a 100644 --- a/src/mainboard/google/geralt/gpio.h +++ b/src/mainboard/google/geralt/gpio.h @@ -13,6 +13,11 @@ #define GPIO_GSC_AP_INT_ODL GPIO(GPIO00) #define GPIO_XHCI_INIT_DONE GPIO(DPI_CK) +#define GPIO_AP_EDP_BKLTEN GPIO(GPIO01) +#define GPIO_EDP_BL_PWM_1V8 GPIO(DISP_PWM1) +#define GPIO_EDP_HPD_1V8 GPIO(GPIO17) +#define GPIO_EN_PP3300_EDP_DISP_X GPIO(DSI1_LCM_RST) + void setup_chromeos_gpios(void); #endif diff --git a/src/mainboard/google/geralt/mainboard.c b/src/mainboard/google/geralt/mainboard.c index ddcb1bb..b2367b6 100644 --- a/src/mainboard/google/geralt/mainboard.c +++ b/src/mainboard/google/geralt/mainboard.c @@ -1,14 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <device/device.h> #include <soc/bl31.h> #include <soc/msdc.h> #include <soc/usb.h> +#include "display.h" #include "gpio.h" static void mainboard_init(struct device *dev) { + if (display_init_required()) { + if (configure_display() < 0) + printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); + } + mtk_msdc_configure_emmc(true); mtk_msdc_configure_sdcard(); setup_usb_host(); -- To view, visit https://review.coreboot.org/c/coreboot/+/68490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Gerrit-Change-Number: 68490 Gerrit-PatchSet: 11 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8188: Update mtcmos settings for display and audio
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68489 ) Change subject: soc/mediatek/mt8188: Update mtcmos settings for display and audio ...................................................................... soc/mediatek/mt8188: Update mtcmos settings for display and audio - For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are required. - For audio, it requires powering on adsp_ao_pwr_con, adsp_infra_pwr_con and audio_pwr_con. - Add new power domain data `ext_buck_iso_bits` for buck isolation control. BUG=b:244208960 TEST=access display registers successfully. Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/mtcmos.h M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/include/soc/spm.h A src/soc/mediatek/mt8188/mtcmos.c 5 files changed, 58 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/mtcmos.h b/src/soc/mediatek/common/include/soc/mtcmos.h index ce8e13e..75f1c38 100644 --- a/src/soc/mediatek/common/include/soc/mtcmos.h +++ b/src/soc/mediatek/common/include/soc/mtcmos.h @@ -8,10 +8,14 @@ u32 pwr_sta_mask; u32 sram_pdn_mask; u32 sram_ack_mask; + u32 ext_buck_iso_bits; u32 caps; }; -#define SCPD_SRAM_ISO (1U << 0) +#define SCPD_SRAM_ISO BIT(0) +#define SCPD_EXT_BUCK_ISO BIT(1) + +void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd); void mtcmos_power_on(const struct power_domain_data *pd); void mtcmos_adsp_power_on(void); diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index 52bd468..2f4bd22 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -14,11 +14,19 @@ PWR_RST_B = 1U << 0 }; +__weak void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd) +{ + /* do nothing */ +} + void mtcmos_power_on(const struct power_domain_data *pd) { write32(&mtk_spm->poweron_config_set, (SPM_PROJECT_CODE << 16) | (1U << 0)); + if (pd->caps & SCPD_EXT_BUCK_ISO) + mtcmos_set_scpd_ext_buck_iso(pd); + setbits32(pd->pwr_con, PWR_ON); setbits32(pd->pwr_con, PWR_ON_2ND); diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index ded5dfc..83914e8 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/mt6359p.c mt6359p.c +ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif_spi.c pmif_spi.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h index 9c5a807..240805c6 100644 --- a/src/soc/mediatek/mt8188/include/soc/spm.h +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -986,30 +986,12 @@ static const struct power_domain_data disp[] = { { - .pwr_con = &mtk_spm->vppsys0_pwr_con, - .pwr_sta_mask = BIT(11), - .sram_pdn_mask = BIT(8), - .sram_ack_mask = BIT(12), - }, - { .pwr_con = &mtk_spm->vdosys0_pwr_con, .pwr_sta_mask = BIT(13), .sram_pdn_mask = BIT(8), .sram_ack_mask = BIT(12), }, { - .pwr_con = &mtk_spm->vppsys1_pwr_con, - .pwr_sta_mask = BIT(12), - .sram_pdn_mask = BIT(8), - .sram_ack_mask = BIT(12), - }, - { - .pwr_con = &mtk_spm->vdosys1_pwr_con, - .pwr_sta_mask = BIT(14), - .sram_pdn_mask = BIT(8), - .sram_ack_mask = BIT(12), - }, - { .pwr_con = &mtk_spm->edp_tx_pwr_con, .pwr_sta_mask = BIT(17), .sram_pdn_mask = BIT(8), @@ -1019,14 +1001,21 @@ static const struct power_domain_data audio[] = { { - .pwr_con = &mtk_spm->adsp_pwr_con, + .pwr_con = &mtk_spm->adsp_ao_pwr_con, + .pwr_sta_mask = BIT(10), + .ext_buck_iso_bits = BIT(10), + .caps = SCPD_EXT_BUCK_ISO, + }, + { + .pwr_con = &mtk_spm->adsp_infra_pwr_con, .pwr_sta_mask = BIT(10), .sram_pdn_mask = BIT(8), .sram_ack_mask = BIT(12), + .caps = SCPD_SRAM_ISO, }, { .pwr_con = &mtk_spm->audio_pwr_con, - .pwr_sta_mask = BIT(8), + .pwr_sta_mask = BIT(6), .sram_pdn_mask = BIT(8), .sram_ack_mask = BIT(12), }, diff --git a/src/soc/mediatek/mt8188/mtcmos.c b/src/soc/mediatek/mt8188/mtcmos.c new file mode 100644 index 0000000..3143b01 --- /dev/null +++ b/src/soc/mediatek/mt8188/mtcmos.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/mtcmos.h> +#include <soc/spm.h> + +void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd) +{ + clrbits32(&mtk_spm->ext_buck_iso, pd->ext_buck_iso_bits); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Gerrit-Change-Number: 68489 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8188: Add eDP support for firmware display
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68488 ) Change subject: soc/mediatek/mt8188: Add eDP support for firmware display ...................................................................... soc/mediatek/mt8188: Add eDP support for firmware display MT8188 supports eDP as internal display interface. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/dp_intf.c M src/soc/mediatek/mt8188/include/soc/addressmap.h 3 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 63c7f4a..ded5dfc 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-y += ../common/emi.c @@ -51,6 +52,7 @@ BL31_MAKEARGS += PLAT=mt8188 CPPFLAGS_common += -Isrc/soc/mediatek/mt8188/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include MT8188_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8188 diff --git a/src/soc/mediatek/mt8188/dp_intf.c b/src/soc/mediatek/mt8188/dp_intf.c new file mode 100644 index 0000000..911cf6f --- /dev/null +++ b/src/soc/mediatek/mt8188/dp_intf.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/addressmap.h> +#include <soc/dp_intf.h> + +const struct mtk_dpintf dpintf_data = { + .regs = (void *)(DP_INTF0_BASE), + .color_format = MTK_DPINTF_COLOR_FORMAT_RGB, + .yc_map = MTK_DPINTF_OUT_YC_MAP_RGB, + .bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS, + .channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB, + .input_mode = MTK_DPINTF_INPUT_MODE_1P, +}; diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index 904e77e..da95952 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -96,9 +96,11 @@ DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000, DISP_DITHER0_BASE = IO_PHYS + 0x0C007000, DISP_OVL1_BASE = IO_PHYS + 0x0C00A000, + DP_INTF0_BASE = IO_PHYS + 0x0C015000, DISP_MUTEX_BASE = IO_PHYS + 0x0C016000, DISP_POSTMASK0_BASE = IO_PHYS + 0x0C01A000, VDOSYS0_BASE = IO_PHYS + 0x0C01D000, SMI_LARB0 = IO_PHYS + 0x0C022000, + EDP_BASE = IO_PHYS + 0x0C500000, }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/68488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6 Gerrit-Change-Number: 68488 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: soc/mediatek/mt8188: Add ddp driver to support eDP output
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68487 ) Change subject: soc/mediatek/mt8188: Add ddp driver to support eDP output ...................................................................... soc/mediatek/mt8188: Add ddp driver to support eDP output Add DDP (display data path) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings to MT8188 to support multi-layer display. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Nathan Lu <nathan.lu(a)mediatek.com> Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68487 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/ddp.c M src/soc/mediatek/mt8188/include/soc/addressmap.h A src/soc/mediatek/mt8188/include/soc/ddp.h 4 files changed, 483 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index d446d5a..63c7f4a 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += ../common/auxadc.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c ramstage-y += ../common/dpm.c diff --git a/src/soc/mediatek/mt8188/ddp.c b/src/soc/mediatek/mt8188/ddp.c new file mode 100644 index 0000000..8d2d43a --- /dev/null +++ b/src/soc/mediatek/mt8188/ddp.c @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <device/mmio.h> +#include <edid.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +static void disp_config_main_path_connection(void) +{ + /* ovl0 */ + write32(&mmsys_cfg->mmsys_ovl_mout_en, + DISP_OVL0_TO_DISP_RDMA0); + write32(&mmsys_cfg->mmsys_dp_intf0_sel_in, + SEL_IN_DP_INTF0_FROM_DISP_DITHER0); + write32(&mmsys_cfg->mmsys_dither0_sel_out, + SEL_OUT_DISP_DITHER0_TO_DP_INTF0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DP_INTF0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DP_INTF0 | (MUTEX_SOF_DP_INTF0 << 7)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_layer_smi_id_en(u32 idx) +{ + setbits32(&disp_ovl[idx]->datapath_con, BIT(0)); +} + +static void ovl_layer_gclast_en(u32 idx) +{ + setbits32(&disp_ovl[idx]->datapath_con, BIT(24)); + setbits32(&disp_ovl[idx]->datapath_con, BIT(25)); +} + +static void ovl_layer_output_clamp_en(u32 idx) +{ + setbits32(&disp_ovl[idx]->datapath_con, BIT(26)); +} + +static void ovl_layer_en(u32 idx) +{ + setbits32(&disp_ovl[idx]->en, BIT(0)); +} + +static void ccorr_config(u32 width, u32 height) +{ + struct disp_ccorr_regs *const regs = disp_ccorr; + + write32(&regs->size, width << 16 | height); + clrsetbits32(&regs->cfg, PQ_ENGINE_EN, PQ_RELAY_MODE); + write32(&regs->en, PQ_EN); +} + +static void aal_config(u32 width, u32 height) +{ + struct disp_aal_regs *const regs = disp_aal; + + write32(&regs->size, width << 16 | height); + write32(&regs->output_size, width << 16 | height); + clrsetbits32(&regs->cfg, PQ_ENGINE_EN, PQ_RELAY_MODE); + write32(&regs->en, PQ_EN); +} + +static void gamma_config(u32 width, u32 height) +{ + struct disp_gamma_regs *const regs = disp_gamma; + + write32(&regs->size, width << 16 | height); + setbits32(&regs->cfg, PQ_RELAY_MODE); + write32(&regs->en, PQ_EN); +} + +static void postmask_config(u32 width, u32 height) +{ + struct disp_postmask_regs *const regs = disp_postmask; + + write32(&regs->size, width << 16 | height); + setbits32(&regs->cfg, PQ_RELAY_MODE); + write32(&regs->en, PQ_EN); +} + +static void dither_config(u32 width, u32 height) +{ + struct disp_dither_regs *const regs = disp_dither; + + write32(&regs->size, width << 16 | height); + setbits32(&regs->cfg, PQ_RELAY_MODE); + write32(&regs->en, PQ_EN); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx; + const u32 pixel_clk = width * height * vrefresh; + + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff); + ovl_layer_smi_id_en(idx); + ovl_layer_gclast_en(idx); + ovl_layer_output_clamp_en(idx); + ovl_layer_en(idx); + } + + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + ccorr_config(width, height); + aal_config(width, height); + gamma_config(width, height); + postmask_config(width, height); + dither_config(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + + /* Turn off M4U port. */ + write32p(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0, 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + printk(BIOS_DEBUG, "%s: display resolution: %dx%d@%d bpp %d\n", + __func__, width, height, vrefresh, bpp); + + if (!vrefresh) { + if (!width || !height) + vrefresh = 60; + else + vrefresh = edid->mode.pixel_clock * 1000 / + ((width + edid->mode.hbl) * + (height + edid->mode.vbl)); + + printk(BIOS_WARNING, "%s: vrefresh is not provided; using %d\n", + __func__, vrefresh); + } + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); +} diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index 55a1497..904e77e 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -88,5 +88,17 @@ I2C6_BASE = IO_PHYS + 0x01EC1000, EFUSE_BASE = IO_PHYS + 0x01F20000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + DISP_OVL0_BASE = IO_PHYS + 0x0C000000, + DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, + DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, + DISP_CCORR0_BASE = IO_PHYS + 0x0C004000, + DISP_AAL0_BASE = IO_PHYS + 0x0C005000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000, + DISP_DITHER0_BASE = IO_PHYS + 0x0C007000, + DISP_OVL1_BASE = IO_PHYS + 0x0C00A000, + DISP_MUTEX_BASE = IO_PHYS + 0x0C016000, + DISP_POSTMASK0_BASE = IO_PHYS + 0x0C01A000, + VDOSYS0_BASE = IO_PHYS + 0x0C01D000, + SMI_LARB0 = IO_PHYS + 0x0C022000, }; #endif diff --git a/src/soc/mediatek/mt8188/include/soc/ddp.h b/src/soc/mediatek/mt8188/include/soc/ddp.h new file mode 100644 index 0000000..26f0151 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/ddp.h @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef _SOC_MEDIATEK_MT8188_DDP_H_ +#define _SOC_MEDIATEK_MT8188_DDP_H_ + +#include <soc/addressmap.h> +#include <soc/ddp_common.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 1 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10c; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11c; /* 0x11C */ + u32 mmsys_cg_con2; /* 0x120 */ + u32 mmsys_cg_set2; /* 0x124 */ + u32 mmsys_cg_clr2; /* 0x128 */ + u32 reserved_0x12c[885]; /* 0x12C */ + u32 reserved_0xf00; /* 0xF00 */ + u32 reserved_0xf04; /* 0xF04 */ + u32 reserved_0xf08; /* 0xF08 */ + u32 reserved_0xf0c; /* 0xF0C */ + u32 reserved_0xf10; /* 0xF10 */ + u32 mmsys_ovl_mout_en; /* 0xF14 */ + u32 reserved_0xf18; /* 0xF18 */ + u32 reserved_0xf1c; /* 0xF1C */ + u32 reserved_0xf20; /* 0xF20 */ + u32 reserved_0xf24; /* 0xF24 */ + u32 reserved_0xf28; /* 0xF28 */ + u32 reserved_0xf2c; /* 0xF2C */ + u32 reserved_0xf30; /* 0xF30 */ + u32 mmsys_sel_in; /* 0xF34 */ + u32 mmsys_sel_out; /* 0xF38 */ + u32 reserved_0xf3c; /* 0xF3C */ + u32 reserved_0xf40; /* 0xF40 */ + u32 mmsys_dsi0_sel_in; /* 0xF44 */ + u32 reserved_0xf48; /* 0xF48 */ + u32 mmsys_dp_intf0_sel_in; /* 0xF4C */ + u32 reserved_0xf50; /* 0xF50 */ + u32 reserved_0xf54; /* 0xF54 */ + u32 mmsys_dither0_sel_out; /* 0xF58 */ +}; +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); +check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x120); +check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF14); + +static struct mmsys_cfg_regs *const mmsys_cfg = (void *)VDOSYS0_BASE; + +/* + * DISP_REG_CONFIG_MMSYS_CG_CON0 + * Configures free-run vdo0_clks gating 0 + * - 0: Enable clock + * - 1: Clock gating + */ +enum { + CG_CON0_DISP_OVL0 = BIT(0), + CG_CON0_DISP_CCORR0 = BIT(4), + CG_CON0_DISP_MUTEX0 = BIT(6), + CG_CON0_DISP_GAMMA0 = BIT(8), + CG_CON0_DISP_DITHER0 = BIT(10), + CG_CON0_DISP_RDMA0 = BIT(19), + CG_CON0_DISP_DSI0 = BIT(21), + CG_CON0_DISP_DSC_WRAP0 = BIT(23), + CG_CON0_DISP_VPP_MERGE0 = BIT(24), + CG_CON0_DISP_DP_INTF0 = BIT(25), + CG_CON0_DISP_AAL0 = BIT(26), + CG_CON0_DISP_COLOR0 = BIT(29), + + CG_CON0_DISP_ALL = CG_CON0_DISP_MUTEX0 | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_GAMMA0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_DP_INTF0, + CG_CON0_ALL = 0xffffffff +}; + +/* + * DISP_REG_CONFIG_MMSYS_CG_CON1 + * Configures free-run clock gating 0 + * - 0: Enable clock + * - 1: Clock gating + */ +enum { + CG_CON1_DISP_POSTMASK0 = BIT(0), + CG_CON1_SMI_GALS = BIT(10), + CG_CON1_SMI_COMMON = BIT(11), + CG_CON1_SMI_EMI = BIT(12), + CG_CON1_SMI_IOMMU = BIT(13), + CG_CON1_SMI_LARB = BIT(14), + CG_CON1_SMI_RSI = BIT(15), + + CG_CON1_DISP_ALL = CG_CON1_DISP_POSTMASK0 | + CG_CON1_SMI_GALS | + CG_CON1_SMI_COMMON | + CG_CON1_SMI_EMI | + CG_CON1_SMI_IOMMU | + CG_CON1_SMI_LARB | + CG_CON1_SMI_RSI, + CG_CON1_ALL = 0xffffffff +}; + +/* + * DISP_REG_CONFIG_MMSYS_CG_CON2 + * Configures free-run clock gating 0 + * - 0: Enable clock + * - 1: Clock gating + */ +enum { + CG_CON2_DSI_DSI0 = BIT(0), + CG_CON2_DPI_DPI0 = BIT(8), + CG_CON2_DP_INTF0 = BIT(16), + + CG_CON2_DISP_ALL = CG_CON2_DP_INTF0, + CG_CON2_ALL = 0xffffffff +}; + +enum { + DISP_OVL0_GO_BLEND = BIT(0), + DISP_OVL0_GO_BG = BIT(1), + DISP_OVL0_TO_DISP_RDMA0 = BIT(0), + DITHER0_MOUT_DSI0 = BIT(0), +}; + + +enum { + SEL_IN_DSI0_FROM_DSC_WRAP0_OUT = (0 << 0), + SEL_IN_DSI0_FROM_DISP_DITHER0 = (1 << 0), +}; + +enum { + SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT = (0 << 0), + SEL_IN_DP_INTF0_FROM_VPP_MERGE = (1 << 0), + SEL_IN_DP_INTF0_FROM_DISP_DITHER0 = (3 << 0), +}; + +enum { + SEL_OUT_DISP_DITHER0_TO_DSC_WRAP0_IN = (0 << 0), + SEL_OUT_DISP_DITHER0_TO_DSI0 = (1 << 0), + SEL_OUT_DISP_DITHER0_TO_VPP_MERGE0 = (6 << 0), + SEL_OUT_DISP_DITHER0_TO_DP_INTF0 = (7 << 0), +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(0), + MUTEX_MOD_DISP_RDMA0 = BIT(2), + MUTEX_MOD_DISP_COLOR0 = BIT(3), + MUTEX_MOD_DISP_CCORR0 = BIT(4), + MUTEX_MOD_DISP_AAL0 = BIT(5), + MUTEX_MOD_DISP_GAMMA0 = BIT(6), + MUTEX_MOD_DISP_DITHER0 = BIT(7), + MUTEX_MOD_DISP_POSTMASK0 = BIT(24), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | + MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_POSTMASK0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, + MUTEX_SOF_DP_INTF0 = 3, +}; + +struct disp_ccorr_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[27]; + u32 shadow; +}; +check_member(disp_ccorr_regs, shadow, 0xa0); + +struct disp_gamma_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_gamma_regs, size, 0x30); + +struct disp_aal_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[47]; + u32 shadow; + u32 reserved3[249]; + u32 output_size; +}; +check_member(disp_aal_regs, shadow, 0xf0); +check_member(disp_aal_regs, output_size, 0x4d8); + +struct disp_postmask_regs { + u32 en; + u32 reserved0[7]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_postmask_regs, size, 0x30); + +struct disp_dither_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[51]; + u32 shadow; +}; +check_member(disp_dither_regs, shadow, 0x100); + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), + PQ_ENGINE_EN = BIT(1), +}; + +static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; +static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; +static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; +static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; +static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +enum { + SMI_LARB_PORT_L0_OVL_RDMA0 = 0xF88, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/68487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388 Gerrit-Change-Number: 68487 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Rename SPM register
by Yu-Ping Wu (Code Review) 25 Oct '22

25 Oct '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68486 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: Rename SPM register ...................................................................... soc/mediatek/mt8188: Rename SPM register The SPM register at offset 0x0 is often named as poweron_config_set in previous MediaTek SoCs. To use common driver, we rename it from poweron_config_en to poweron_config_set. BUG=none TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/include/soc/spm.h M src/soc/mediatek/mt8188/pmif_clk.c M src/soc/mediatek/mt8188/spm.c 3 files changed, 26 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h index 734a810..9c5a807 100644 --- a/src/soc/mediatek/mt8188/include/soc/spm.h +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -437,7 +437,7 @@ }; struct mtk_spm_regs { - u32 poweron_config_en; + u32 poweron_config_set; u32 spm_power_on_val0; u32 spm_power_on_val1; u32 spm_clk_con; diff --git a/src/soc/mediatek/mt8188/pmif_clk.c b/src/soc/mediatek/mt8188/pmif_clk.c index aac9b7b..0a94325 100644 --- a/src/soc/mediatek/mt8188/pmif_clk.c +++ b/src/soc/mediatek/mt8188/pmif_clk.c @@ -106,8 +106,8 @@ pmif_ulposc_config(); /* enable APB clock swinf */ - if (!READ32_BITFIELD(&mtk_spm->poweron_config_en, BCLK_CG_EN)) - SET32_BITFIELDS(&mtk_spm->poweron_config_en, BCLK_CG_EN, 1, + if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN)) + SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1, PROJECT_CODE, 0xb16); /* turn on ulposc */ diff --git a/src/soc/mediatek/mt8188/spm.c b/src/soc/mediatek/mt8188/spm.c index fd4648f..c87d1f0 100644 --- a/src/soc/mediatek/mt8188/spm.c +++ b/src/soc/mediatek/mt8188/spm.c @@ -440,7 +440,7 @@ /* set clock path for SPM */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x7ff); /* enable register control */ - write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + write32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); /* init power control register, dram will set this register */ write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); write32(&mtk_spm->pcm_pwr_io_en, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/68486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0 Gerrit-Change-Number: 68486 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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