Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68641 )
Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> I got confused myself. Using stage cache is indeed a performance optimisation, but in order for that to be secure it has to reside in TSEG. So not using stage cache has no security implications.
Oh ok, in that case what do you think about this change?
> Also whether reading from cached SPI flash (with prefetch enabled) is faster than reading uncached DRAM is probably platform dependent.
I understand, and platforms can enable the config if it benefits them. But I still think disabling it is a better default. If SPI if faster than uncached memory on some platforms and slower on others, then let's say on average across platforms they're the same speed (is that reasonable?).
If we add postcar to stage cache we do 2 operations on boot (read from SPI, write to memory) and 1 operation on resume (read from memory).
If we don't add postcar, we only do 1 operation on boot, and 1 on resume.
So on average we'd save some boot time while not affecting resume time.
> I think it's not a bad idea to attempt skipping it as indeed FSP puts things in memory and not coreboot.
Ok, makes sense. We should do that if/when we decide to enable caching in romstage then. But for nissa at least, the total boot time will still be better if we don't add postcar to stage cache at all (either via this CL or selecting NO_STAGE_CACHE).
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68768 )
Change subject: lib/coreboot_table: Simplify API to set up lb_serial
......................................................................
Patch Set 7:
(1 comment)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/68768/comment/24bc7a87_da897af4
PS7, Line 102: struct lb_serial new_serial = get_lb_serial();
: /* Use the base address as a proxy for an invalid struct */
: if (new_serial.baseaddr == 0)
: return;
:
: serial = (struct lb_serial *)lb_new_record(header);
: memcpy(serial, &new_serial, sizeof(*serial));
: serial->tag = LB_TAG_SERIAL;
: serial->size = sizeof(*serial);
: if (serial->type == LB_SERIAL_TYPE_IO_MAPPED)
: lb_add_console(LB_TAG_CONSOLE_SERIAL8250, header);
: else
: lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, header);
It's true we can return a struct, but the implementation above is
- using a hint baseaddr=0 implies invalid
- assuming the get_lb_serial will only fill partial data
- overwriting the size
If we're going to change the APIs, I'd rather redefine it as:
int get_lb_serial(struct lb_serial *serial) {
serial->type = ...
return 0;
}
And then you can do here:
struct lb_serial new_serial = {0};
new_serial.tag = LB_TAG_SERIAL;
new_serial.size = sizeof(new_serial);
if (!get_lb_serial(&new_serial))
return;
// allocate the new record, copy serial etc
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Change subject: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68626/comment/c84a6a0b_ef0d8d67
PS1, Line 10: a converged firmware image
> What is a “converged firmware image”?
The firmware image can support two platform (alder lake and raptor lake). Thanks.
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Change subject: coreboot_tables: Drop uart PCI addr
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/intel/alderlake: Add Raptor Lake device IDs
......................................................................
Patch Set 7: Code-Review+2
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Change subject: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/skyrim/var/frostflow: Update devicetree setting
......................................................................
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Change subject: NOTFORMERGE/WIP/POC Use FDT as payload handoff instead lb_tables
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Were there any discussions about this that I missed (if so would you mind linking to them)? Can you explain who needs this and why, what's the overall goal? (I know there have been vague discussions about various new firmware handoff formats from Arm and Intel and others, but if this is related to those I missed the parts where there was suddenly consensus on how it should look, and why that is FDT.)
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Change subject: drivers/intel/fsp2_0: Add support for locating specific HOB instance
......................................................................
Patch Set 4: Verified+1
(1 comment)
File src/drivers/intel/fsp2_0/hand_off_block.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161208):
https://review.coreboot.org/c/coreboot/+/51061/comment/87d7442a_f180272d
PS4, Line 220: return fsp_find_extension_hob_inst_by_guid (guid, size, 0);
space prohibited between function name and open parenthesis '('
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Hello build bot (Jenkins), Jason Glenesk, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68802
to look at the new patch set (#2).
Change subject: mainboard/amd/chausie: Don't use APCB_FT6_Updatable
......................................................................
mainboard/amd/chausie: Don't use APCB_FT6_Updatable
This APCB binary is not used for coreboot builds. Coreboot does not
support RW APCB.
Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com>
---
M src/mainboard/amd/chausie/Makefile.inc
1 file changed, 15 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/68802/2
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