coreboot-gerrit October 2022

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[M] Change in coreboot[master]: soc/intel/common: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68702 ) Change subject: soc/intel/common: Clean up includes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Gerrit-Change-Number: 68702 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:24:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/drivers: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68206 ) Change subject: src/drivers: Clean up includes ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia40678019b2a54deb246dbfbf33ec37a8c3839e4 Gerrit-Change-Number: 68206 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:21:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/device: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68205 ) Change subject: src/device: Clean up includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd78271f2158bdc29ce9ac8d81f46ad8cbe84c5e Gerrit-Change-Number: 68205 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:18:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68204 ) Change subject: cpu/x86: Clean up includes ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01c6651079333686cb0eb68e89e56d7907868124 Gerrit-Change-Number: 68204 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:18:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/cezanne: Factor out common GPP clk req code
by Karthik Ramasubramanian (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68138 ) Change subject: soc/amd/cezanne: Factor out common GPP clk req code ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/pci/Kconfig: https://review.coreboot.org/c/coreboot/+/68138/comment/1c4d7767_8368af43 PS6, Line 16: depends on SOC_AMD_COMMON_BLOCK_PCI Can we `select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ` here instead of in every single SOC Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/68138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Gerrit-Change-Number: 68138 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:17:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68203 ) Change subject: cpu/intel: Clean up includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie760711916c49d275ca49d94b9597fd24b5e7628 Gerrit-Change-Number: 68203 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:17:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: console/post.c: Sort includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68202 ) Change subject: console/post.c: Sort includes ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68202/comment/4be69d6c_4d6c0150 PS1, Line 7: Sorte Sort -- To view, visit https://review.coreboot.org/c/coreboot/+/68202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3faa1baf41ff8f0447d18b131a9c9c225e9fc8a4 Gerrit-Change-Number: 68202 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:17:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/commonlib: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68201 ) Change subject: src/commonlib: Clean up includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieba5a5291209e50dc8b3816efb25bb5b2515fa6a Gerrit-Change-Number: 68201 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:16:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68200 ) Change subject: arch/x86: Clean up includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2db229dec2ed44333faaa8c53f3a2f9d66d52e0 Gerrit-Change-Number: 68200 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:15:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/tigerlake: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68700 ) Change subject: soc/intel/tigerlake: Clean up includes ...................................................................... soc/intel/tigerlake: Clean up includes Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> --- M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/tigerlake/dptf.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/lockdown.c M src/soc/intel/tigerlake/me.c M src/soc/intel/tigerlake/p2sb.c M src/soc/intel/tigerlake/pcie_rp.c M src/soc/intel/tigerlake/retimer.c M src/soc/intel/tigerlake/romstage/systemagent.c M src/soc/intel/tigerlake/spi.c M src/soc/intel/tigerlake/xhci.c 12 files changed, 31 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index b8086a4..5ef9662 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <cpu/cpu.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <stdint.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/tigerlake/dptf.c b/src/soc/intel/tigerlake/dptf.c index 2f0427e..2f4cf5f 100644 --- a/src/soc/intel/tigerlake/dptf.c +++ b/src/soc/intel/tigerlake/dptf.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <drivers/intel/dptf/dptf.h> +#include <stdbool.h> static const struct dptf_platform_info tgl_dptf_platform_info = { .use_eisa_hids = false, diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 301c88a..29f1712 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <bootstate.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> +#include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pci_type.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <intelblocks/xhci.h> diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ef75c56..d7c60be 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -3,7 +3,6 @@ #include <assert.h> #include <console/console.h> #include <device/device.h> -#include <arch/pci_io_cfg.h> #include <cpu/intel/cpu_ids.h> #include <device/pci_ops.h> #include <device/pci.h> diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c index 1e04dc3..2f7cceb 100644 --- a/src/soc/intel/tigerlake/lockdown.c +++ b/src/soc/intel/tigerlake/lockdown.c @@ -10,6 +10,7 @@ #include <intelblocks/cfg.h> #include <intelpch/lockdown.h> #include <soc/pm.h> +#include <stdint.h> static void pmc_lock_pmsync(void) { diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index ea94902..560464f 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> -#include <intelblocks/cse.h> #include <console/console.h> +#include <intelblocks/cse.h> #include <soc/me.h> -#include <stdint.h> +#include <types.h> /* Host Firmware Status Register 2 */ union me_hfsts2 { diff --git a/src/soc/intel/tigerlake/p2sb.c b/src/soc/intel/tigerlake/p2sb.c index fc8323a..1a0f23f 100644 --- a/src/soc/intel/tigerlake/p2sb.c +++ b/src/soc/intel/tigerlake/p2sb.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <intelblocks/p2sb.h> +#include <types.h> void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) { diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c index 57a5cf2..01bca17 100644 --- a/src/soc/intel/tigerlake/pcie_rp.c +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <device/pci_def.h> #include <intelblocks/pcie_rp.h> #include <soc/pci_devs.h> +#include <stdbool.h> #define CPU_CPIE_VW_IDX_BASE 24 diff --git a/src/soc/intel/tigerlake/retimer.c b/src/soc/intel/tigerlake/retimer.c index 09bf112..32cb828 100644 --- a/src/soc/intel/tigerlake/retimer.c +++ b/src/soc/intel/tigerlake/retimer.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <drivers/intel/usb4/retimer/retimer.h> #include <intelblocks/tcss.h> +#include <stdint.h> int retimer_get_index_for_typec(uint8_t typec_port) { diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c index bedc192..2393e6a 100644 --- a/src/soc/intel/tigerlake/romstage/systemagent.c +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -6,6 +6,7 @@ * Chapter number: 3 */ +#include <commonlib/bsd/helpers.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/romstage.h> diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index d68b146..47b3b33 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -6,9 +6,10 @@ * Chapter number: 7 */ -#include <intelblocks/spi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/spi.h> #include <soc/pci_devs.h> +#include <stdint.h> #define PSF_SPI_DESTINATION_ID_H 0x23b0 #define PSF_SPI_DESTINATION_ID 0x23a8 diff --git a/src/soc/intel/tigerlake/xhci.c b/src/soc/intel/tigerlake/xhci.c index 6f095fa..af201aa 100644 --- a/src/soc/intel/tigerlake/xhci.c +++ b/src/soc/intel/tigerlake/xhci.c @@ -3,6 +3,7 @@ #include <device/pci_type.h> #include <intelblocks/xhci.h> #include <soc/pci_devs.h> +#include <stddef.h> #define PCH_XHCI_USB2_PORT_STATUS_REG 0x480 #define PCH_XHCI_USB3_PORT_STATUS_REG 0x520 -- To view, visit https://review.coreboot.org/c/coreboot/+/68700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Gerrit-Change-Number: 68700 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2022