coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboard
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68770 ) Change subject: mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboard ...................................................................... mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboard Move the Raydium touchscreen to the baseboard devicetree. Since only the liara variant uses a level IRQ as I2C devices are supposed to, all other board variants still override this to use an edge IRQ which were added as a workaround to make the touchscreen work on the other devices. Right now it's unclear to me if that edge IRQ workaround was only needed temporarily and can now be removed, so I'll keep it as it was for now. If this turns out to be no longer needed on the other variants, the overrides can be dropped in the future. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68770 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/kahlee/variants/baseboard/devicetree.cb M src/mainboard/google/kahlee/variants/liara/overridetree.cb 2 files changed, 35 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 2f6e0da..fc74d77 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -85,6 +85,18 @@ end device ref i2c_3 on chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "probed" = "1" diff --git a/src/mainboard/google/kahlee/variants/liara/overridetree.cb b/src/mainboard/google/kahlee/variants/liara/overridetree.cb index 1d750b8..7b1c2d3 100644 --- a/src/mainboard/google/kahlee/variants/liara/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/overridetree.cb @@ -50,18 +50,4 @@ device i2c 2c on end end end - device ref i2c_3 on - chip drivers/i2c/generic - register "hid" = ""RAYD0001"" - register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 39 on end - end - end end #chip soc/amd/stoneyridge -- To view, visit https://review.coreboot.org/c/coreboot/+/68770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4 Gerrit-Change-Number: 68770 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: console: Add an SoC-specific post-code call
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68545 ) Change subject: console: Add an SoC-specific post-code call ...................................................................... console: Add an SoC-specific post-code call Add a post-code call that SoCs can hook to output or save in any way that is specific to that SoC. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68545 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/console/post.c M src/include/console/console.h 2 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/console/post.c b/src/console/post.c index 1d99a2e..35e8779 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -5,6 +5,7 @@ /* Write POST information */ void __weak arch_post_code(uint8_t value) { } +void __weak soc_post_code(uint8_t value) { } /* Some mainboards have very nice features beyond just a simple display. * They can override this function. @@ -18,6 +19,8 @@ for displaying POST so keep it first. */ arch_post_code(value); + soc_post_code(value); + if (CONFIG(CONSOLE_POST)) printk(BIOS_INFO, "POST: 0x%02x\n", value); diff --git a/src/include/console/console.h b/src/include/console/console.h index e4090af..49bce61 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -16,6 +16,7 @@ void post_code(u8 value); void mainboard_post(u8 value); void arch_post_code(u8 value); +void soc_post_code(uint8_t value); void __noreturn die(const char *fmt, ...); #define die_with_post_code(value, fmt, ...) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/68545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Gerrit-Change-Number: 68545 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/x86/smm: Add PCI BAR store functionality
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Arthur Heymans, Robert Zieba, Nico Huber, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 ) Change subject: cpu/x86/smm: Add PCI BAR store functionality ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67931/comment/8c138c1c_6cd3135f PS2, Line 9: n certain cases data within protected memmory areas like SMRAM could : be leaked or modified if an attacker remaps PCI BARs to point within : that area. > > I thought the hardware makes sure that you cannot put BARs where memory resides. […] Thanks Nico, great explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 17:14:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/mp_init: adjust timeout for 2nd SIPI
by Jonathan Zhang (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Arthur Heymans, Christian Walter, Angel Pons. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68262 ) Change subject: cpu/x86/mp_init: adjust timeout for 2nd SIPI ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68262/comment/ea06611d_5df1ba20 PS6, Line 9: luanched > launched Done Patchset: PS6: Thanks for the review. File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/68262/comment/39571017_a46b7a64 PS6, Line 154: BIOS_DEBUG > This should probably be BIOS_TRACE Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Gerrit-Change-Number: 68262 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 25 Oct 2022 17:12:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: MAINTAINERS: Update EC section
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Martin L Roth, Michael Niewöhner. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68708 ) Change subject: MAINTAINERS: Update EC section ...................................................................... Patch Set 1: (1 comment) File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/68708/comment/bf8ef403_b71faa74 PS1, Line 730: Orphaned ECs > IMO "orphaned" could be misleading. […] It's just what it's called: S: Status, one of the following: Supported: Someone is continuously paid to look after this and a reaction to review requests can be expected within a few days, a month at most. Maintained: Someone actually looks after it and a reaction to review requests can usually be expected within a few weeks. Odd Fixes: It has a maintainer but they don't have time to do much other than throw the odd patch in. See below.. Orphan: No current maintainer [but maybe you could take the role as you write your new code]. Obsolete: Old code. Something tagged obsolete generally means it has been replaced by a better system and you should be using that. See https://review.coreboot.org/c/coreboot/+/68708/1/MAINTAINERS#935 -- To view, visit https://review.coreboot.org/c/coreboot/+/68708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia93e8da9898903ae92873a07fb0af2a2aa76e8b4 Gerrit-Change-Number: 68708 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 17:12:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/mp_init: adjust timeout for 2nd SIPI
by Jonathan Zhang (Code Review) 25 Oct '22

25 Oct '22

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68786 ) Change subject: cpu/x86/mp_init: adjust timeout for 2nd SIPI ...................................................................... cpu/x86/mp_init: adjust timeout for 2nd SIPI Adjust timeout for 2nd SIPI to satisfy some to-be-launched server processors. Add a trace print to display how long it takes for the APs to be ready. This facilitates trouble shooting and trend analysis. Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> temp Change-Id: I29f9aba1d0256b7b3458a78b0b8a8b4b294c4482 Signed-off-by: jon(a)meta.com --- M src/cpu/x86/mp_init.c 1 file changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/68786/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index df74d24..c3936c06 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -151,6 +151,7 @@ } /* APs ready before timeout */ + printk(BIOS_TRACE, "APs are ready after %dus\n", delayed); return CB_SUCCESS; } @@ -468,7 +469,7 @@ if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) return CB_ERR; - /* Wait for CPUs to check in up to 200 us. */ + /* Wait for CPUs to check in. */ wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); } @@ -477,7 +478,7 @@ return CB_ERR; /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */) != CB_SUCCESS) { + if (wait_for_aps(num_aps, ap_count, 400000 /* 400 ms */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); return CB_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/68786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29f9aba1d0256b7b3458a78b0b8a8b4b294c4482 Gerrit-Change-Number: 68786 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ec/google/chromec: Host event support of DTTS
by Karthik Ramasubramanian (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67793 ) Change subject: ec/google/chromec: Host event support of DTTS ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67793/comment/f945e5db_9302822f PS11, Line 10: 1/2/9 Instead of magic numbers, can you please add human-readable event description like lid close, lid open etc. -- To view, visit https://review.coreboot.org/c/coreboot/+/67793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Gerrit-Change-Number: 67793 Gerrit-PatchSet: 11 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 17:11:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
by Meera Ravindranath (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Nick Vaccaro, Divagar Mohandass. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 ) Change subject: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS ...................................................................... Patch Set 9: (3 comments) File src/soc/intel/alderlake/include/soc/ufs.h: https://review.coreboot.org/c/coreboot/+/68251/comment/75bfc3b1_0d7a1bb3 PS8, Line 26: 0x1B0C > 0x1b0c Done https://review.coreboot.org/c/coreboot/+/68251/comment/64d0a8af_84da8e04 PS8, Line 27: 0x1E30 > 0x1e30 Done File src/soc/intel/common/block/acpi/acpi/ufs.asl: https://review.coreboot.org/c/coreboot/+/68251/comment/8b4df17c_d9cf9e6b PS8, Line 67: PCH_PWRM_BASE_SIZE > nit: won't this fit in line above? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Gerrit-Change-Number: 68251 Gerrit-PatchSet: 9 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Daniil Lunev <dlunev(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Daniil Lunev <dlunev(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 17:10:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: MAINTAINERS: Make Misc Fixes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Martin L Roth, Paul Menzel. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68709 ) Change subject: MAINTAINERS: Make Misc Fixes ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68709/comment/dde79028_e274280a PS1, Line 7: MAINTAINERS: Misc Fixes > Please make it a statement by adding a verb (in imperative mood): […] Done https://review.coreboot.org/c/coreboot/+/68709/comment/9fd8b6a9_07b95842 PS1, Line 11: Remover > Remove Done https://review.coreboot.org/c/coreboot/+/68709/comment/36a32610_b2e99240 PS1, Line 12: - Remove maintainers who don't have +2 rights in gerrit. > Hmm, is that necessary? Do the persons removed know about that? Yeah, if they can't mark something as +2, they aren't: 1) Regular coreboot contributors. 2) Very effective as maintainers. I'm removing a maintainer who has reviewed 3 patches, all of which were the maintainers list and has never pushed a coreboot patch. That's just silly - they're obviously *NOT* a maintainer. If they want to be notified about patches, they can set up their profile to get an email when something in their area changes. I've updated the instructions saying that they need to have +2 rights to be a maintainer. -- To view, visit https://review.coreboot.org/c/coreboot/+/68709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc Gerrit-Change-Number: 68709 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 25 Oct 2022 17:09:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromec: Host event support of DTTS
by Karthik Ramasubramanian (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Tim Wawrzynczak, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67793 ) Change subject: ec/google/chromec: Host event support of DTTS ...................................................................... Patch Set 11: (1 comment) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/67793/comment/5e77e1dc_4b2d9e40 PS11, Line 20: #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) Do we really need this conditional check? Same for all the places that we introduced. Reason: This ASL code that applies to all SoCs has SoC specific check. Also DPTC method is accessed only if it is present. Hence the question. -- To view, visit https://review.coreboot.org/c/coreboot/+/67793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Gerrit-Change-Number: 67793 Gerrit-PatchSet: 11 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 17:09:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022