coreboot-gerrit October 2022

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[S] Change in coreboot[master]: payloads: Make PAYLOAD_NONE a bool outside of the choice
by Sean Rhodes (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Martin L Roth, Matt DeVillier. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68595 ) Change subject: payloads: Make PAYLOAD_NONE a bool outside of the choice ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I932c65630261a5b39809abf4dfbda5bf932c6684 Gerrit-Change-Number: 68595 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:20:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/emulation/riscv: Limit DRAM size
by Arthur Heymans (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Philipp Hug, ron minnich. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68843 ) Change subject: mb/emulation/riscv: Limit DRAM size ...................................................................... mb/emulation/riscv: Limit DRAM size Qemu only limits 16GiB of address space and gets confused when probing for addresses much higher. Therefore limit the amount of dram we wish to probe. Change-Id: Ib8555de361d1129d3d1995f056518c576f055515 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-riscv/Kconfig 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/68843/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 0af309a..5891595 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -44,9 +44,11 @@ int default 1 +# Qemu maps MMIO at ALIGN_UP(top_of_mem, 16 * GiB) +# To avoid confusing the dram probing algoritm, avoid large dram sizes (16G - 1m) config DRAM_SIZE_MB int - default 32768 + default 16383 config OPENSBI_PLATFORM string -- To view, visit https://review.coreboot.org/c/coreboot/+/68843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8555de361d1129d3d1995f056518c576f055515 Gerrit-Change-Number: 68843 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: lib/ramdetect: Limit probe size to function argument
by Arthur Heymans (Code Review) 25 Oct '22

25 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68842 ) Change subject: lib/ramdetect: Limit probe size to function argument ...................................................................... lib/ramdetect: Limit probe size to function argument This avoids probing above the function argument where other things than DRAM could be mapped. Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/ramdetect.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/68842/1 diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 328ca07..25bdbe9 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -57,9 +57,12 @@ msb = MIN(msb, MAX_ADDRESSABLE_SPACE); /* Compact binary search. */ - for (i = msb; i >= 0; i--) + for (i = msb; i >= 0; i--) { + if ((discovered | (1ULL << i)) > probe_size) + continue; if (probe_mb(dram_start, (discovered | (1ULL << i)))) discovered |= (1ULL << i); + } saved_result = discovered; printk(BIOS_DEBUG, "RAMDETECT: Found %zu MiB RAM\n", discovered); -- To view, visit https://review.coreboot.org/c/coreboot/+/68842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Gerrit-Change-Number: 68842 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: riscv: add smp support for exception handler
by Arthur Heymans (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Philipp Hug, Xiang W, ron minnich. Hello Xiang W, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68841 to review the following change. Change subject: riscv: add smp support for exception handler ...................................................................... riscv: add smp support for exception handler Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/payload.c M src/arch/riscv/trap_util.S 2 files changed, 114 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68841/1 diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 3097ad1..3bf9d5e 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -6,6 +6,7 @@ #include <arch/encoding.h> #include <arch/smp/atomic.h> #include <console/console.h> +#include <mcall.h> #include <vm.h> /* Run OpenSBI and let OpenSBI hand over control to the payload */ @@ -66,6 +67,7 @@ die("wrong privilege level for payload"); break; } + write_csr(mscratch, MACHINE_STACK_TOP()); write_csr(mstatus, status); write_csr(mepc, doit); asm volatile( diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index f1c4c4d..2dd0d63 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -7,124 +7,115 @@ #include <mcall.h> .macro restore_regs - # restore x registers - LOAD x1,1*REGBYTES(a0) - LOAD x2,2*REGBYTES(a0) - LOAD x3,3*REGBYTES(a0) - LOAD x4,4*REGBYTES(a0) - LOAD x5,5*REGBYTES(a0) - LOAD x6,6*REGBYTES(a0) - LOAD x7,7*REGBYTES(a0) - LOAD x8,8*REGBYTES(a0) - LOAD x9,9*REGBYTES(a0) - LOAD x11,11*REGBYTES(a0) - LOAD x12,12*REGBYTES(a0) - LOAD x13,13*REGBYTES(a0) - LOAD x14,14*REGBYTES(a0) - LOAD x15,15*REGBYTES(a0) - LOAD x16,16*REGBYTES(a0) - LOAD x17,17*REGBYTES(a0) - LOAD x18,18*REGBYTES(a0) - LOAD x19,19*REGBYTES(a0) - LOAD x20,20*REGBYTES(a0) - LOAD x21,21*REGBYTES(a0) - LOAD x22,22*REGBYTES(a0) - LOAD x23,23*REGBYTES(a0) - LOAD x24,24*REGBYTES(a0) - LOAD x25,25*REGBYTES(a0) - LOAD x26,26*REGBYTES(a0) - LOAD x27,27*REGBYTES(a0) - LOAD x28,28*REGBYTES(a0) - LOAD x29,29*REGBYTES(a0) - LOAD x30,30*REGBYTES(a0) - LOAD x31,31*REGBYTES(a0) - # restore a0 last - LOAD x10,10*REGBYTES(a0) + # restore x registers + LOAD x1, 1 * REGBYTES(sp) + LOAD x3, 3 * REGBYTES(sp) + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) +.endm - - .endm .macro save_tf - # save gprs - STORE x1,1*REGBYTES(x2) - STORE x3,3*REGBYTES(x2) - STORE x4,4*REGBYTES(x2) - STORE x5,5*REGBYTES(x2) - STORE x6,6*REGBYTES(x2) - STORE x7,7*REGBYTES(x2) - STORE x8,8*REGBYTES(x2) - STORE x9,9*REGBYTES(x2) - STORE x10,10*REGBYTES(x2) - STORE x11,11*REGBYTES(x2) - STORE x12,12*REGBYTES(x2) - STORE x13,13*REGBYTES(x2) - STORE x14,14*REGBYTES(x2) - STORE x15,15*REGBYTES(x2) - STORE x16,16*REGBYTES(x2) - STORE x17,17*REGBYTES(x2) - STORE x18,18*REGBYTES(x2) - STORE x19,19*REGBYTES(x2) - STORE x20,20*REGBYTES(x2) - STORE x21,21*REGBYTES(x2) - STORE x22,22*REGBYTES(x2) - STORE x23,23*REGBYTES(x2) - STORE x24,24*REGBYTES(x2) - STORE x25,25*REGBYTES(x2) - STORE x26,26*REGBYTES(x2) - STORE x27,27*REGBYTES(x2) - STORE x28,28*REGBYTES(x2) - STORE x29,29*REGBYTES(x2) - STORE x30,30*REGBYTES(x2) - STORE x31,31*REGBYTES(x2) + # save gprs + STORE x1, 1 * REGBYTES(sp) + STORE x3, 3 * REGBYTES(sp) + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) - # get sr, epc, badvaddr, cause - csrrw t0,mscratch,x0 - csrr s0,mstatus - csrr t1,mepc - csrr t2,mbadaddr - csrr t3,mcause - STORE t0,2*REGBYTES(x2) - STORE s0,32*REGBYTES(x2) - STORE t1,33*REGBYTES(x2) - STORE t2,34*REGBYTES(x2) - STORE t3,35*REGBYTES(x2) + # get sr, epc, badvaddr, cause + csrr t0, mscratch + bnez t0, 1f # t0 == 0, trap come from current program + # t0 != 0, t0 is saved old sp + add t0, sp, MENTRY_FRAME_SIZE +1: + csrr s0, mstatus + csrr t1, mepc + csrr t2, mbadaddr + csrr t3, mcause + STORE t0, 2 * REGBYTES(sp) + STORE s0, 32 * REGBYTES(sp) + STORE t1, 33 * REGBYTES(sp) + STORE t2, 34 * REGBYTES(sp) + STORE t3, 35 * REGBYTES(sp) - # get faulting insn, if it wasn't a fetch-related trap - li x5,-1 - STORE x5,36*REGBYTES(x2) + # get faulting insn, if it wasn't a fetch-related trap + li x5, -1 + STORE x5, 36 * REGBYTES(sp) +.endm - .endm - -.globl estack - .text - - .global trap_entry - .align 2 # four byte alignment, as required by mtvec + .text + .global trap_entry + # four byte alignment, as required by mtvec + .align 2 trap_entry: - csrw mscratch, sp + # mscratch is initialized to 0 + # when exiting coreboot, write sp to mscratch + csrrw sp, mscratch, sp + bnez sp, 1f # sp == 0, trap come from current program + csrrw sp, mscratch, sp +1: + addi sp, sp, -MENTRY_FRAME_SIZE + save_tf - # SMP isn't supported yet, to avoid overwriting the same stack with different - # harts that handle traps at the same time. - # someday this gets fixed. - //csrr sp, mhartid - csrr sp, 0xf14 -.Lsmp_hang: - bnez sp, .Lsmp_hang + mv a0, sp + jal trap_handler - # Use a different stack than in the main context, to to avoid overwriting - # stack data. - # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if - # the previous mode was M, because it would be a very bad idea to use a stack - # pointer provided by unprivileged code! - la sp, _estack - addi sp, sp, -2048 # 2 KiB is half of the stack space - addi sp, sp, -MENTRY_FRAME_SIZE - - save_tf - move a0,sp - jal trap_handler - -trap_return: - csrr a0, mscratch restore_regs - # go back to the previous mode + addi sp, sp, MENTRY_FRAME_SIZE + + csrrw sp, mscratch, sp + bnez sp, 1f + csrrw sp, mscratch, sp +1: mret -- To view, visit https://review.coreboot.org/c/coreboot/+/68841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Gerrit-Change-Number: 68841 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Xiang W <wxjstz(a)126.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/riscv/romstage: Start from assembly
by Arthur Heymans (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Philipp Hug, ron minnich. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68840 ) Change subject: arch/riscv/romstage: Start from assembly ...................................................................... arch/riscv/romstage: Start from assembly Without this it would use the exception handler from the previous stage. Change-Id: I79d875aca6cd0cffe482e4ebb5f388af0adf6aed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/include/arch/header.ld D src/arch/riscv/include/arch/stages.h A src/arch/riscv/romstage.S D src/arch/riscv/romstage.c 5 files changed, 52 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/68840/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 574fb62..bb500de 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -90,7 +90,7 @@ ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) -romstage-y += romstage.c +romstage-y += romstage.S # Build the romstage diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index ddb618c..bca852c 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -8,8 +8,4 @@ to_load PT_LOAD; } -#if ENV_BOOTBLOCK || ENV_RAMSTAGE ENTRY(_start) -#else -ENTRY(stage_entry) -#endif diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h deleted file mode 100644 index f9de2b5..0000000 --- a/src/arch/riscv/include/arch/stages.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ARCH_STAGES_H -#define __ARCH_STAGES_H - -#include <main_decl.h> - -void stage_entry(int hart_id, void *fdt) - __attribute__((section(".text.stage_entry"))); - -#endif diff --git a/src/arch/riscv/romstage.S b/src/arch/riscv/romstage.S new file mode 100644 index 0000000..bf85acb --- /dev/null +++ b/src/arch/riscv/romstage.S @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/encoding.h> +#include <bits.h> +#include <mcall.h> + +.section ".text._start", "ax", %progbits +.globl _start +_start: + # initialize stack point for each hart + # and the stack must be page-aligned. + # 0xDEADBEEF used to check stack overflow + csrr a0, mhartid + la t0, _stack + slli t1, a0, RISCV_PGSHIFT + add t0, t0, t1 + li t1, 0xDEADBEEF + STORE t1, 0(t0) + li t1, RISCV_PGSIZE - HLS_SIZE + add sp, t0, t1 + + # initialize hart-local storage + csrr a0, mhartid + call hls_init + + li a0, CONFIG_RISCV_WORKING_HARTID + call smp_pause + + # initialize entry of interrupt/exception + la t0, trap_entry + csrw mtvec, t0 + + # clear any pending interrupts + csrwi mip, 0 + + # set up the mstatus register + call mstatus_init + tail main diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c deleted file mode 100644 index c7340b2..0000000 --- a/src/arch/riscv/romstage.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Entry points must be placed at the location the previous stage jumps - * to (the lowest address in the stage image). This is done by giving - * stage_entry() its own section in .text and placing it first in the - * linker script. - */ - -#include <arch/stages.h> -#include <arch/smp/smp.h> -#include <mcall.h> - -void stage_entry(int hart_id, void *fdt) -{ - HLS()->hart_id = hart_id; - HLS()->fdt = fdt; - smp_pause(CONFIG_RISCV_WORKING_HARTID); - - main(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/68840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d875aca6cd0cffe482e4ebb5f388af0adf6aed Gerrit-Change-Number: 68840 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/x86/riscv: Use 'all' target to include files in all stages
by Arthur Heymans (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Philipp Hug, ron minnich. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68839 ) Change subject: arch/x86/riscv: Use 'all' target to include files in all stages ...................................................................... arch/x86/riscv: Use 'all' target to include files in all stages This adds a few new files to romstage, that will be needed in follow-up patches. Change-Id: I2ba84e0becee883b5becf12e51f40734cad83d7d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/Makefile.inc 1 file changed, 35 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/68839/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index bbbdeb0..574fb62 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -41,31 +41,34 @@ COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(simple_riscv_flags) -print-libgcc-file-name) +## All stages + +all-y += trap_util.S +all-y += trap_handler.c +all-y += fp_asm.S +all-y += misaligned.c +all-y += sbi.c +all-y += mcall.c +all-y += virtual_memory.c +all-y += boot.c +all-y += smp.c +all-y += misc.c +all-$(ARCH_RISCV_PMP) += pmp.c +all-y += \ + $(top)/src/lib/memchr.c \ + $(top)/src/lib/memcmp.c \ + $(top)/src/lib/memcpy.c \ + $(top)/src/lib/memmove.c \ + $(top)/src/lib/memset.c +all-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c + + ################################################################################ ## bootblock ################################################################################ ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y) bootblock-y = bootblock.S -bootblock-y += trap_util.S -bootblock-y += trap_handler.c -bootblock-y += fp_asm.S -bootblock-y += misaligned.c -bootblock-y += sbi.c -bootblock-y += mcall.c -bootblock-y += virtual_memory.c -bootblock-y += boot.c -bootblock-y += smp.c -bootblock-y += misc.c -bootblock-$(ARCH_RISCV_PMP) += pmp.c -bootblock-y += \ - $(top)/src/lib/memchr.c \ - $(top)/src/lib/memcmp.c \ - $(top)/src/lib/memcpy.c \ - $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c - -bootblock-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -87,19 +90,7 @@ ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) -romstage-y += boot.c romstage-y += romstage.c -romstage-y += misc.c -romstage-$(ARCH_RISCV_PMP) += pmp.c -romstage-y += smp.c -romstage-y += \ - $(top)/src/lib/memchr.c \ - $(top)/src/lib/memcmp.c \ - $(top)/src/lib/memcpy.c \ - $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c - -romstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c # Build the romstage @@ -123,28 +114,9 @@ ramstage-y = ramstage-y += ramstage.S -ramstage-y += mcall.c -ramstage-y += trap_util.S -ramstage-y += trap_handler.c -ramstage-y += fp_asm.S -ramstage-y += misaligned.c -ramstage-y += sbi.c -ramstage-y += virtual_memory.c -ramstage-y += misc.c -ramstage-y += smp.c -ramstage-y += boot.c ramstage-y += tables.c ramstage-y += payload.c -ramstage-$(ARCH_RISCV_PMP) += pmp.c ramstage-y += fit_payload.c -ramstage-y += \ - $(top)/src/lib/memchr.c \ - $(top)/src/lib/memcmp.c \ - $(top)/src/lib/memcpy.c \ - $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c - -ramstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c $(eval $(call create_class_compiler,rmodules,riscv)) -- To view, visit https://review.coreboot.org/c/coreboot/+/68839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ba84e0becee883b5becf12e51f40734cad83d7d Gerrit-Change-Number: 68839 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/x86/mp_init: adjust timeout for 2nd SIPI
by Arthur Heymans (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jonathan Zhang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68786 ) Change subject: cpu/x86/mp_init: adjust timeout for 2nd SIPI ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/68786/comment/6beb738c_9b7ecc36 PS1, Line 154: BIOS_TRACE This does not exist in coreboot. Also printing the message affects the time needed before the second sipi. -- To view, visit https://review.coreboot.org/c/coreboot/+/68786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29f9aba1d0256b7b3458a78b0b8a8b4b294c4482 Gerrit-Change-Number: 68786 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:16:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
by 9elements QA (Code Review) 25 Oct '22

25 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68667 ) Change subject: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130702 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130701 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130700 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130699 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130698 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130697 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130696 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130695 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130694 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130693 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130692 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130691 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130690 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130689 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130688 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130687 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Gerrit-Change-Number: 68667 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:00:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES
by Fred Reitberger (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68818 ) Change subject: soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Gerrit-Change-Number: 68818 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 18:52:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd,google: move fch_irq_routing struct definition to soc/amd
by Fred Reitberger (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68817 ) Change subject: mb/amd,google: move fch_irq_routing struct definition to soc/amd ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Gerrit-Change-Number: 68817 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 18:47:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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