coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: device/mmio: add clr/setbitsXp macros
by Michael Niewöhner (Code Review) 25 Oct '22

25 Oct '22

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68790 ) Change subject: device/mmio: add clr/setbitsXp macros ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/68790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b10ccab97c3a372051050b28ada854baec91d18 Gerrit-Change-Number: 68790 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:30:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: provide S0ix hooks in PEP for ECs
by Michael Niewöhner (Code Review) 25 Oct '22

25 Oct '22

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68789 ) Change subject: soc/intel/common: provide S0ix hooks in PEP for ECs ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/68789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef Gerrit-Change-Number: 68789 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:29:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/acpi: provide PTS/WAK hooks for ECs
by Michael Niewöhner (Code Review) 25 Oct '22

25 Oct '22

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68788 ) Change subject: soc/intel/common/acpi: provide PTS/WAK hooks for ECs ...................................................................... Patch Set 1: Code-Review+2 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/68788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I687254362a896baa590959bd01ae49579ec12c94 Gerrit-Change-Number: 68788 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:29:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpigen: add prototypes for some functions
by Michael Niewöhner (Code Review) 25 Oct '22

25 Oct '22

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68787 ) Change subject: acpigen: add prototypes for some functions ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/68787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If89f9569c33949995d3b45a5f871ff2cb84a6610 Gerrit-Change-Number: 68787 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:29:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE
by Robert Zieba (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68866 ) Change subject: soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE ...................................................................... soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE Currently the GPP clk req configuration code assumes that the size of the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that code to use the `ARRAY_SIZE` macro instead. BRANCH=guybrush BUG=b:250009974 TEST=Ran on nipperkin device, verified that clk req settings are correct. Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/soc/amd/cezanne/fch.c 1 file changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/68866/1 diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 7227d20..1ceb8bc 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -153,7 +153,8 @@ uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); - pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); -- To view, visit https://review.coreboot.org/c/coreboot/+/68866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7 Gerrit-Change-Number: 68866 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
by Robert Zieba (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Martin Roth, Fred Reitberger, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68139 to look at the new patch set (#7). Change subject: soc/amd/mendocino: Enable GPP clk req disabling for disabled devices ...................................................................... soc/amd/mendocino: Enable GPP clk req disabling for disabled devices Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/mainboard/amd/chausie/Makefile.inc M src/mainboard/google/skyrim/Makefile.inc M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fch.c 4 files changed, 27 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/68139/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/68139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Gerrit-Change-Number: 68139 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/cezanne: Factor out common GPP clk req code
by Robert Zieba (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68138 to look at the new patch set (#7). Change subject: soc/amd/cezanne: Factor out common GPP clk req code ...................................................................... soc/amd/cezanne: Factor out common GPP clk req code Factor out the `gpp_dxio_update_clk_req_config` function as it will be useful for other AMD SoCs. BUG=b:250009974 TEST=Ran on nipperkin device, verified clk req settings match enabled devices Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c A src/soc/amd/common/block/include/amdblocks/pci_clk_req.h M src/soc/amd/common/block/pci/Kconfig M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/pcie_clk_req.c 6 files changed, 142 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/68138/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/68138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Gerrit-Change-Number: 68138 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/emulation/riscv: Limit DRAM size
by build bot (Jenkins) (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Philipp Hug, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68843 ) Change subject: mb/emulation/riscv: Limit DRAM size ...................................................................... Patch Set 1: (1 comment) File src/mainboard/emulation/qemu-riscv/Kconfig: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161264): https://review.coreboot.org/c/coreboot/+/68843/comment/60a3d72f_7d2b7c04 PS1, Line 48: # To avoid confusing the dram probing algoritm, avoid large dram sizes (16G - 1m) 'algoritm' may be misspelled - perhaps 'algorithm'? -- To view, visit https://review.coreboot.org/c/coreboot/+/68843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8555de361d1129d3d1995f056518c576f055515 Gerrit-Change-Number: 68843 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:21:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/clevo/l140cu: drop System76 EC
by Michael Niewöhner (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Angel Pons, Michal Zygowski. Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Angel Pons, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59816 to look at the new patch set (#3). Change subject: mb/clevo/l140cu: drop System76 EC ...................................................................... mb/clevo/l140cu: drop System76 EC Drop System76 EC, since the ODM board does not use it. Clevo EC FW support will be added and hooked up cleanly in the follow-up changes. Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/Kconfig D src/mainboard/clevo/cml-u/acpi/gpe.asl D src/mainboard/clevo/cml-u/acpi/mainboard.asl D src/mainboard/clevo/cml-u/acpi/sleep.asl M src/mainboard/clevo/cml-u/dsdt.asl M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 6 files changed, 13 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/59816/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5 Gerrit-Change-Number: 59816 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: lib/ramdetect: Limit probe size to function argument
by build bot (Jenkins) (Code Review) 25 Oct '22

25 Oct '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68842 ) Change subject: lib/ramdetect: Limit probe size to function argument ...................................................................... Patch Set 1: (2 comments) File src/lib/ramdetect.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161263): https://review.coreboot.org/c/coreboot/+/68842/comment/52babb0e_af7936b2 PS1, Line 61: if ((discovered | (1ULL << i)) > probe_size) suspect code indent for conditional statements (16, 20) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161263): https://review.coreboot.org/c/coreboot/+/68842/comment/13c883c9_fd89a72f PS1, Line 62: continue; Statements should start on a tabstop -- To view, visit https://review.coreboot.org/c/coreboot/+/68842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Gerrit-Change-Number: 68842 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Oct 2022 19:20:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2022