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Hello Felix Singer,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/clevo/l140cu: PECI idle workaround
......................................................................
mb/clevo/l140cu: PECI idle workaround
According to Intel doc# 575683 the PECI bus should be low when idle and
is pulled up by clients with strong drive. However, for unknown reasons
the bus stays high on this board, blocking s0ix entry.
The PECI reference schematic in the ASPEED AST2400 BMC datasheet
(actually not related to this board) says that a pull-down is *required*
for the idle state.
This might be just a requirement of this BMC, since this is nowhere
documented in Intel datasheets, schematics or elsewhere. However,
configuring a weak pull-down (20 k) on the PECI pad indeed solves this
problem for now.
Change-Id: Ib5a6b0ad3553c2cf795037d6a1982102bcb04644
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/variants/l140cu/gpio.c
1 file changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/68793/2
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Michael Niewöhner has uploaded a new patch set (#18) to the change originally created by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/62498 )
Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
......................................................................
mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
Add support for the Clevo NV4x series of laptops (NV4xMZ/MB/ME).
These laptops have an Intel TigerLake-U processor and an ITE IT5570E
embedded controller, and with come optional NVIDIA Optimus hybrid
graphics depending on model. `x` in device name indicates chassis
color.
devicetree based on system76/galp5.
Working:
- Booting UEFI OS via TianoCore payload from MrChromebox's fork
- All hotkeys - except Touchpad Toggle, which requires tweak in OS
- s0ix / modern standby, including when a USB-C is device connected
- Onboard discrete TPM 2.0
- USB-A and USB-C ports including TBT, HDMI, SD card, audio
- Ethernet, CNVi Wi-Fi / PCIe Wi-Fi, Bluetooth
Not working:
- ACPI UCSI interface - possibly due to bug in EC FW
- dTPM detection when PTT is enabled in the ME region
Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc
Co-authored-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Co-authored-by: Michael Niewöhner <foss(a)mniewoehner.de>
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/tgl-u/Kconfig
M src/mainboard/clevo/tgl-u/Kconfig.name
A src/mainboard/clevo/tgl-u/variants/nv40mz/acpi/variant.asl
A src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt
A src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt
A src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb
A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c
A src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c
11 files changed, 672 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/18
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Change subject: mb/clevo/l140cu: make use of the new clevo/it5570e ec driver
......................................................................
mb/clevo/l140cu: make use of the new clevo/it5570e ec driver
Hook up the new EC driver.
Tested:
- Fn hotkeys work (brightness, display, volume, tp toggle, ...)
- Display lid
- Sleep/wake
- Camera (including Fn toggle)
- Bluetooth (both CNVi and PCIe card)
- Wifi (both CNVi and PCIe card)
Change-Id: I28ac401ada2945bb58fe862895458b10fed505fe
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/Kconfig
M src/mainboard/clevo/cml-u/Makefile.inc
M src/mainboard/clevo/cml-u/bootblock.c
M src/mainboard/clevo/cml-u/cmos.default
M src/mainboard/clevo/cml-u/cmos.layout
M src/mainboard/clevo/cml-u/dsdt.asl
A src/mainboard/clevo/cml-u/fadt.c
A src/mainboard/clevo/cml-u/smihandler.c
A src/mainboard/clevo/cml-u/variants/l140cu/acpi/variant.asl
M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
10 files changed, 111 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/68795/2
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Hello Felix Singer,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/clevo/l140cu: enable S0ix
......................................................................
mb/clevo/l140cu: enable S0ix
Enable S0ix for the board, as done in vendor fw.
Change-Id: Ifdf93e1e599e7cc03fc02297eafb49d34b1f6172
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
1 file changed, 13 insertions(+), 0 deletions(-)
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Attention is currently required from: Michał Żygowski, Michał Kopeć.
Hello Michał Żygowski, Michał Kopeć,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68791
to look at the new patch set (#2).
Change subject: ec/clevo/it5570e: add driver for EC used on various Clevo laptops
......................................................................
ec/clevo/it5570e: add driver for EC used on various Clevo laptops
This adds a driver for the ITE IT5570E EC in combination with Clevo
vendor EC firmware. The interface is mostly identical on various laptop
models. Thus, we have implemented one common driver to support them all.
The following features were implemented:
- Basics like battery, ac, etc.
- Suspend/hibernate support: S0ix, S3*, S4/S5
- Save/restore of keyboard backlight level during S0ix without the need
for Clevo vendor software (ControlCenter)
- Flexicharger
- Fn keys (backlight, volume, airplane etc.)
- Various configuration options via Kconfig / CMOS options
* Note: S3 support works at least on L140CU (Cometlake), but it's not
enabled for this board because S0ix is used.
Not implemented, yet:
- Type-C UCSI: the EC firmware seems to be buggy (with vendor fw, too)
- dGPU support is WIP
An example of how this driver can be hooked up by a board can be seen in
the follow-up patch, where support for the L140MU is added.
Known issue with the touchpad toggle:
The touchpad toggle (Fn-F1) has two modes, Ctrl-Alt-F9 mode and keycodes
0xf7/0xf8 mode. Ctrl-Alt-F9 is the native touchpad toggle shortcut on
Windows. On Linux this would switch to virtual console 9, if enabled.
Thus, one should use the keycodes mode and add udev rules as specified in
https://docs.dasharo.com/variants/clevo_nv41/post_install/ .
If VT9 is disabled, Ctrl-Alt-F9 mode could be used to set up a keyboard
shortcut command toggling the touchpad.
Testing the various functionalities of this EC driver was done in the
changes hooking up this driver for the boards.
Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0
Co-authored-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Co-authored-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Co-authored-by: Michael Niewöhner <foss(a)mniewoehner.de>
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
A src/ec/clevo/it5570e/Kconfig
A src/ec/clevo/it5570e/Makefile.inc
A src/ec/clevo/it5570e/acpi/ac.asl
A src/ec/clevo/it5570e/acpi/battery.asl
A src/ec/clevo/it5570e/acpi/buttons.asl
A src/ec/clevo/it5570e/acpi/common.asl
A src/ec/clevo/it5570e/acpi/ec.asl
A src/ec/clevo/it5570e/acpi/ec_queries.asl
A src/ec/clevo/it5570e/acpi/ec_ram.asl
A src/ec/clevo/it5570e/acpi/hid.asl
A src/ec/clevo/it5570e/acpi/lid.asl
A src/ec/clevo/it5570e/chip.h
A src/ec/clevo/it5570e/commands.c
A src/ec/clevo/it5570e/commands.h
A src/ec/clevo/it5570e/early_init.c
A src/ec/clevo/it5570e/early_init.h
A src/ec/clevo/it5570e/ec.c
A src/ec/clevo/it5570e/ec.h
A src/ec/clevo/it5570e/i2ec.c
A src/ec/clevo/it5570e/i2ec.h
A src/ec/clevo/it5570e/smbios.c
A src/ec/clevo/it5570e/smihandler.c
A src/ec/clevo/it5570e/smm.h
A src/ec/clevo/it5570e/ssdt.c
24 files changed, 2,065 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/68791/2
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Michael Niewöhner has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/68790 )
Change subject: device/mmio: add clr/setbitsXp macros
......................................................................
device/mmio: add clr/setbitsXp macros
Add clr/setbits*p macros as pendant to read/write*p.
Change-Id: I5b10ccab97c3a372051050b28ada854baec91d18
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/include/device/mmio.h
1 file changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/68790/2
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Michael Niewöhner has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/68789 )
Change subject: soc/intel/common: provide S0ix hooks in PEP for ECs
......................................................................
soc/intel/common: provide S0ix hooks in PEP for ECs
Provide PEP display notification hooks for ECs.
Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/pep.c
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/68789/2
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Michael Niewöhner has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/68788 )
Change subject: soc/intel/common/acpi: provide PTS/WAK hooks for ECs
......................................................................
soc/intel/common/acpi: provide PTS/WAK hooks for ECs
Provide PTS/WAK hooks for ECs like we do for mainboards.
Change-Id: I687254362a896baa590959bd01ae49579ec12c94
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/acpi/platform.asl
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/68788/2
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Attention is currently required from: Lance Zhao, Tim Wawrzynczak.
Hello Lance Zhao, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: acpigen: add prototypes for some functions
......................................................................
acpigen: add prototypes for some functions
Add include prototypes for:
- acpigen_emit_simple_namestring
- acpigen_write_field_name
They will be used in a follow-up change.
Change-Id: If89f9569c33949995d3b45a5f871ff2cb84a6610
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/acpigen.c
M src/include/acpi/acpigen.h
2 files changed, 20 insertions(+), 2 deletions(-)
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Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 )
Change subject: cpu/x86/smm: Add PCI BAR store functionality
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67931/comment/0b6d0cad_0cd00cb8
PS2, Line 11: This commit adds support to the existing SMM to allow storing
: PCI BARs in SMRAM and then later retrieved.
> > Done […]
Done in the sense that it seems like the original question has been answered between this comment https://review.coreboot.org/c/coreboot/+/67931/comments/c2ba1641_2770009d and the discussion here.
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/67931/comment/f77e66ac_bc8b57d5
PS5, Line 195:
: config SMM_PCI_BAR_STORE
: bool
: depends on SMM_CHIPSET_STORE
: help
: This option enables support for storing PCI BARs in SMRAM so they
: can't be tampered with.
:
: config SMM_PCI_BAR_STORE_NUM_SLOTS
: int
: default 8
: help
: Number of slots available to store PCI BARs in SMRAM
> I would remove this, since it's not really generic
I think the BAR store part of this is generic enough to leave in. The Intel XHCI event logging code is susceptible to the same problem and could use it as well. Though maybe I should get rid of the chipset store aspect? Because if the BAR store part of this is usable for AMD and Intel then maybe that should go directly into the smm runtime struct and not be contained in a chipset store.
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