coreboot-gerrit October 2022

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[M] Change in coreboot[master]: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
by Meera Ravindranath (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Haribalaraman Ramasubramanian, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Meera Ravindranath, Nick Vaccaro, Divagar Mohandass. Hello build bot (Jenkins), Subrata Banik, Haribalaraman Ramasubramanian, Tim Wawrzynczak, Rizwan Qureshi, Daniil Lunev, Divagar Mohandass, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68251 to look at the new patch set (#9). Change subject: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS ...................................................................... soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS a) Add LTR disqualification in D3 to ensure PMC ignores LTR from UFS IP as it is infinite. b) Remove LTR disqualification in _PS0 to ensure PMC stops ignoring LTR from UFS IP during D3 exit. c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply this LTR WA. BUG=b:252975357 TEST=build and boot nirwen and see no issues in PLT runs Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/ufs.h M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi/ufs.asl 4 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/68251/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/68251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Gerrit-Change-Number: 68251 Gerrit-PatchSet: 9 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Daniil Lunev <dlunev(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Daniil Lunev <dlunev(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: MAINTAINERS: Make Misc Fixes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Martin L Roth. Martin Roth has uploaded a new patch set (#2) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/68709 ) Change subject: MAINTAINERS: Make Misc Fixes ...................................................................... MAINTAINERS: Make Misc Fixes - X86 architecture is maintained, so mark it as such. - Legacy AMD chips are supported for odd fixes. - Remove maintainers whose emails are bouncing. - Remove maintainers who don't have +2 rights in gerrit. - According to the instructions, we should use S: Orphan, not Orphaned. - Update incorrect email addresses. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc --- M MAINTAINERS 1 file changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/68709/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc Gerrit-Change-Number: 68709 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: MAINTAINERS: Update instructions
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68705 ) Change subject: MAINTAINERS: Update instructions ...................................................................... MAINTAINERS: Update instructions Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I0e06ac5f92109757143897f3d331aeea0cefe4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68705 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M MAINTAINERS 1 file changed, 24 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 131aea6..4627a58 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14,27 +14,17 @@ easier on the maintainers. Not all of these guidelines matter for every trivial patch so apply some common sense. -1. Always _test_ your changes, however small, on at least 1 or - 2 people, preferably many more. -2. Try to release a few ALPHA test versions to gerrit. Announce - them onto the coreboot mailing list and IRC channel and await - results. This is especially important on coreboot core changes, - but also for device drivers, because often that's the only way - you will find things like the fact revision 3 chipset needs - a magic fix you didn't know about, or some clown changed the - chips on a board and not its name. (Don't laugh!) +1. Make sure your changes compile correctly in multiple configurations. In + particular check that changes work for various boards in the tree that + it affects: -3. Make sure your changes compile correctly in multiple - configurations. In particular check that changes work for all - boards in the tree (use abuild!) + Test with: `util/abuild/abuild -c $(nproc) -t vendor/boardname` -4. When you are happy with a change make it generally available for +2. When you are happy with a change make it generally available for testing in gerrit and await feedback. -5. Make your patch available through coreboot's gerrit code review - system, and add the relevant maintainer from this list as a code - reviewer. Be prepared to get your changes sent back with seemingly +3. Be prepared to get your changes sent back with seemingly silly requests about formatting and variable names. These aren't as silly as they seem. One job the maintainers do is to keep things looking the same. Sometimes this means that the clever @@ -45,36 +35,27 @@ (util/lint/checkpatch.pl) to catch trival style violations. See https://www.coreboot.org/Coding_Style for guidance here. - PLEASE add the maintainers that are generated by - util/scripts/get_maintainer.pl as reviewers. The results returned - by the script will be best if you have git installed and are - making your changes in a branch derived from coreboot.org's latest - git tree. - - PLEASE try to include any credit lines you want added with the - patch. It avoids people being missed off by mistake and makes - it easier to know who wants adding and who doesn't. - PLEASE document known bugs. If it doesn't work for everything or does something very odd once a month document it. - PLEASE remember that submissions must be made under the terms + ALWAYS remember that submissions are made under the terms of the OSDL certificate of contribution and should include a Signed-off-by: line. The current version of this "Developer's Certificate of Origin" (DCO) is listed at https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure. -6. Make sure you have the right to send any changes you make. If you +4. Make sure you have the right to send any changes you make. If you do changes at work you may find your employer owns the patch not you. -7. Happy hacking. +5. Happy hacking. Descriptions of section entries: M: Maintainer: FullName <address@domain> Must be registered to Gerrit (https://review.coreboot.org/). - Should have experience with upstream coreboot development. + Should have experience with upstream coreboot development and + +2 rights. R: Designated reviewer: FullName <address@domain> These reviewers should be CCed on patches. L: Mailing list that is relevant to this area -- To view, visit https://review.coreboot.org/c/coreboot/+/68705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e06ac5f92109757143897f3d331aeea0cefe4b9 Gerrit-Change-Number: 68705 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/ocp/dmi: set SMBIOS type 0 firmware revision
by Jonathan Zhang (Code Review) 25 Oct '22

25 Oct '22

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68785 ) Change subject: drivers/ocp/dmi: set SMBIOS type 0 firmware revision ...................................................................... drivers/ocp/dmi: set SMBIOS type 0 firmware revision Set smbios type 0 firmware revision. Refer to IPMI v2.0 SPEC, minor revision is defined as BCD encoded so update the format accordingly. TESTED=Execute "dmidecode -t 0" to check corresponding field. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Jonzhang Zhang <jonzhang(a)meta.com> Change-Id: I898662b78d3dbab1861cee6f1b6e148297a5d11b --- M src/drivers/ocp/dmi/smbios.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/68785/1 diff --git a/src/drivers/ocp/dmi/smbios.c b/src/drivers/ocp/dmi/smbios.c index 51c008d..0ac3334 100644 --- a/src/drivers/ocp/dmi/smbios.c +++ b/src/drivers/ocp/dmi/smbios.c @@ -22,6 +22,21 @@ msr_t xeon_sp_ppin[2] = {0}; static bool remote_ppin_done = false; +/* + * Update SMBIOS type 0 ec version. + * For OCP platforms, BMC version is used to represent ec version. + * Refer to IPMI v2.0 spec, minor revision is defined as BCD encoded, + * format it accordingly. + */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + uint8_t bmc_major_revision, bmc_minor_revision; + + ipmi_bmc_version(&bmc_major_revision, &bmc_minor_revision); + *ec_major_revision = bmc_major_revision & 0x7f; /* bit[6:0] Major Firmware Revision */ + *ec_minor_revision = ((bmc_minor_revision / 16) * 10) + (bmc_minor_revision % 16); +} + /* Override SMBIOS type 1 data. */ const char *smbios_system_manufacturer(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/68785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I898662b78d3dbab1861cee6f1b6e148297a5d11b Gerrit-Change-Number: 68785 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/ocp: add VPD processing framework
by Jonathan Zhang (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Marc Jones, Tim Chu. Hello Marc Jones, Tim Chu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/68784 to review the following change. Change subject: drivers/ocp: add VPD processing framework ...................................................................... drivers/ocp: add VPD processing framework Add VPD processing framework to be shared by OCP mainboards: * define VPD configruation items in vpd.h. * add helper functions: ** get_bool_from_vpd() ** get_int_from_vpd_range() Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> --- A src/drivers/ocp/include/vpd.h A src/drivers/ocp/vpd/Kconfig A src/drivers/ocp/vpd/Makefile.inc A src/drivers/ocp/vpd/vpd_util.c 4 files changed, 153 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68784/1 diff --git a/src/drivers/ocp/include/vpd.h b/src/drivers/ocp/include/vpd.h new file mode 100644 index 0000000..fe230ee --- /dev/null +++ b/src/drivers/ocp/include/vpd.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef OCP_VPD_H +#define OCP_VPD_H + +/* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */ +#define FRB2_TIMER "frb2_timer_enable" +#define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */ + +/* VPD variable for setting FRB2 timer countdown value. */ +#define FRB2_COUNTDOWN "frb2_countdown" +/* Default countdown is 15 minutes when the VPD variable is not found */ +#define FRB2_COUNTDOWN_DEFAULT 9000 + +/* VPD variable for setting FRB2 timer action. + 0: No action, 1: hard reset, 2: power down, 3: power cycle */ +#define FRB2_ACTION "frb2_action" +#define FRB2_ACTION_DEFAULT 0 /* Default no action when the VPD variable is not found */ + +/* coreboot log level */ +#define COREBOOT_LOG_LEVEL "coreboot_log_level" +#define COREBOOT_LOG_LEVEL_DEFAULT 4 + +/* Define the VPD keys for UPD variables that can be overwritten */ +#define FSP_LOG "fsp_log_enable" /* 1 or 0: enable or disable FSP SOL log */ +#define FSP_LOG_DEFAULT 1 /* Default value when the VPD variable is not found */ + +/* Select Memory Serial Debug Message Level. + 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto */ +#define FSP_MEM_LOG_LEVEL "fsp_mem_log_lvl" +#define FSP_MEM_LOG_LEVEL_DEFAULT 1 + +/* VPD variable for enabling/disabling MRC promote warning in FSP. + System may upgrade memory training warning to fatal error when enabled. + 0: Disable, 1: Enable */ +#define MRC_PROMOTE_WARNING "mrc_promote_warning" +#define MRC_PROMOTE_WARNING_DEFAULT 1 + +/* SMM log level */ +#define SMM_LOG_LEVEL "smm_log_level" +#define SMM_LOG_LEVEL_DEFAULT 0 /* By default 0 would disable SMM log completely */ + +/* FSP Dfx PMIC secure mode. + 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode */ +#define FSP_PMIC_SECURE_MODE "fsp_pmic_mode" +#define FSP_PMIC_SECURE_MODE_DEFAULT 2 + +enum cxl_memory_mode { + CXL_DISABLED, // 0 + CXL_SYSTEM_MEMORY, // 1 + CXL_SPM,//2 + CXL_MODE_MAX, +}; + +/* CXL mode. 0: Disable CXL, 1: configured as system memory, 2: configured as SPM. */ +#define CXL_MODE "cxl_mode" +#define CXL_MODE_DEFAULT CXL_SYSTEM_MEMORY /* By default configured as system memory */ + +/* Skip TXT lockdown */ +#define SKIP_INTEL_TXT_LOCKDOWN "skip_intel_txt_lockdown" +#define SKIP_INTEL_TXT_LOCKDOWN_DEFAULT 0 + +/* Disable boot drive PCIe root port for testing */ +#define DISABLE_BOOTDRIVE "disable_bootdrive" +#define DISABLE_BOOTDRIVE_DEFAULT 0 /* By default don't disable */ + +/* Skip Global reset so that information in Previous Boot Error Hob won't be cleared */ +#define SKIP_GLOBAL_RESET "skip_global_reset" +#define SKIP_GLOBAL_RESET_DEFAULT 1 + +/* Disable memory poison */ +#define DISABLE_MEM_POISON "disable_mem_poison" +#define DISABLE_MEM_POISON_DEFAULT 0 + +/* Socket 0 core disable bitmask, set 1 to disable core */ +#define CORE_DIS_BITMSK0 "core_disable_bitmask0" +/* Socket 1 core disable bitmask */ +#define CORE_DIS_BITMSK1 "core_disable_bitmask1" + +/* Get VPD key with provided fallback value and min/max ranges */ +int get_int_from_vpd_range(const char *const key, const int fallback, const int min, + const int max); +bool get_bool_from_vpd(const char *const key, const bool fallback); +#endif diff --git a/src/drivers/ocp/vpd/Kconfig b/src/drivers/ocp/vpd/Kconfig new file mode 100644 index 0000000..ebecbe6 --- /dev/null +++ b/src/drivers/ocp/vpd/Kconfig @@ -0,0 +1,6 @@ +config OCP_VPD + bool + default n + depends on VPD + help + It implements functions that get common VPD variables for OCP projects. diff --git a/src/drivers/ocp/vpd/Makefile.inc b/src/drivers/ocp/vpd/Makefile.inc new file mode 100644 index 0000000..d00f27d --- /dev/null +++ b/src/drivers/ocp/vpd/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_OCP_VPD) += vpd_util.c +ramstage-$(CONFIG_OCP_VPD) += vpd_util.c +smm-$(CONFIG_VPD_SMM_SUPPORT) += vpd_util.c diff --git a/src/drivers/ocp/vpd/vpd_util.c b/src/drivers/ocp/vpd/vpd_util.c new file mode 100644 index 0000000..57dbc3c --- /dev/null +++ b/src/drivers/ocp/vpd/vpd_util.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <drivers/ocp/include/vpd.h> + +int get_int_from_vpd_range(const char *const key, const int fallback, const int min, + const int max) +{ + int val = fallback; + + if (!vpd_get_int(key, VPD_RW_THEN_RO, &val)) + printk(BIOS_INFO, "%s: not able to get VPD %s, default set to %d\n", + __func__, key, fallback); + else + printk(BIOS_DEBUG, "%s: VPD %s, got %d\n", __func__, key, val); + + if (val < min || val > max) { + printk(BIOS_INFO, "Invalid VPD %s value, set default value to %d\n", + key, fallback); + val = fallback; + } + + return val; +} + +bool get_bool_from_vpd(const char *const key, const bool fallback) +{ + uint8_t val; + + val = (uint8_t)fallback; + + if (!vpd_get_bool(key, VPD_RW_THEN_RO, &val)) + printk(BIOS_INFO, "%s: not able to get VPD %s, default set to %d\n", + __func__, key, fallback); + else + printk(BIOS_DEBUG, "%s: VPD %s, got %d\n", __func__, key, val); + + + return (bool)val; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Gerrit-Change-Number: 68784 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/x86/smm: Add PCI BAR store functionality
by Nico Huber (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Arthur Heymans, Robert Zieba, Martin Roth, Karthik Ramasubramanian, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 ) Change subject: cpu/x86/smm: Add PCI BAR store functionality ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67931/comment/74e6febd_98d341f3 PS2, Line 9: n certain cases data within protected memmory areas like SMRAM could : be leaked or modified if an attacker remaps PCI BARs to point within : that area. > I thought the hardware makes sure that you cannot put BARs where memory resides. You can, but the device will most likely not work. One attack vector is not so much about what the hardware does with a wrong BAR setting, but what the software (SMI handler) does. Imagine the BAR (register) as a scratch pad, it doesn't matter if the device can work with the value in there. Then, if the SMI handler would read that register (as an address) to access the device, it might acciden- tally access protected memory instead. Another way to see it: the register can be used to pass a pointer into the SMI handler. It shouldn't trust that pointer. -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:56:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/mp_init: adjust timeout for 2nd SIPI
by Christian Walter (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Arthur Heymans, Jonathan Zhang, Angel Pons. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68262 ) Change subject: cpu/x86/mp_init: adjust timeout for 2nd SIPI ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68262/comment/63605ca4_6b756c5b PS6, Line 9: luanched launched File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/68262/comment/ee9e3997_b9709d26 PS6, Line 154: BIOS_DEBUG This should probably be BIOS_TRACE -- To view, visit https://review.coreboot.org/c/coreboot/+/68262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Gerrit-Change-Number: 68262 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:47:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86/smm: Add PCI BAR store functionality
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Arthur Heymans, Robert Zieba, Nico Huber, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 ) Change subject: cpu/x86/smm: Add PCI BAR store functionality ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67931/comment/c7a29aef_eee40eeb PS2, Line 9: n certain cases data within protected memmory areas like SMRAM could : be leaked or modified if an attacker remaps PCI BARs to point within : that area. > Can you do that? I thought the hardware makes sure that you cannot put BARs where memory resides. I'd just remove the 'like smram'. -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:36:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Clean up includes
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68702 ) Change subject: soc/intel/common: Clean up includes ...................................................................... soc/intel/common: Clean up includes Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/intel/common/block/acpi/lpit.c M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/gpio/gpio_dev.c M src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/usb4/pcie.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/smbios.h M src/soc/intel/common/vbt.c 16 files changed, 48 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c index 5b9689c..38a402f 100644 --- a/src/soc/intel/common/block/acpi/lpit.c +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -4,6 +4,7 @@ #include <cpu/intel/msr.h> #include <soc/iomap.h> #include <soc/pmc.h> +#include <stdint.h> unsigned long acpi_fill_lpit(unsigned long current) { diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index 21e3d35..cd1030c 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <acpi/acpigen.h> #include <assert.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> #include <intelblocks/acpi.h> #include <intelblocks/pmc_ipc.h> #include <stdlib.h> +#include <string.h> #include <types.h> #define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" diff --git a/src/soc/intel/common/block/gpio/gpio_dev.c b/src/soc/intel/common/block/gpio/gpio_dev.c index a179473..bea0363 100644 --- a/src/soc/intel/common/block/gpio/gpio_dev.c +++ b/src/soc/intel/common/block/gpio/gpio_dev.c @@ -3,8 +3,8 @@ #include <assert.h> #include <device/device.h> #include <device/gpio.h> -#include <intelblocks/gpio.h> #include <gpio.h> +#include <intelblocks/gpio.h> static struct gpio_operations gpio_ops = { .get = gpio_get, diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c index 1b2a2d1..cef2e57 100644 --- a/src/soc/intel/common/block/gpmr/gpmr.c +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -5,6 +5,7 @@ #include <intelblocks/ioc.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> +#include <types.h> /* GPMR Register read given offset */ uint32_t gpmr_read32(uint16_t offset) diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 63aa800..3093921 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -4,6 +4,7 @@ #define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H #include <device/device.h> +#include <stdint.h> /* * SoC overrides diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index d3fcbde..dd0b0ef 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <device/device.h> #include <device/pci.h> -#include <device/pciexp.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pciexp.h> +#include <stdint.h> #define CACHE_LINE_SIZE 0x10 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index ba49f7c..897cd82 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -2,13 +2,17 @@ #define __SIMPLE_DEVICE__ -#include <device/mmio.h> #include <assert.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> -#include <intelblocks/pcr.h> +#include <device/mmio.h> +#include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pci_type.h> +#include <intelblocks/pcr.h> #include <soc/pci_devs.h> #include <timer.h> +#include <types.h> #if (CONFIG_PCR_BASE_ADDRESS == 0) #error "PCR_BASE_ADDRESS need to be non-zero!" diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c index a3173f3..273d29e 100644 --- a/src/soc/intel/common/block/smbus/smbus_early.c +++ b/src/soc/intel/common/block/smbus/smbus_early.c @@ -4,8 +4,11 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> +#include <device/pci_type.h> #include <intelblocks/smbus.h> #include <soc/pci_devs.h> +#include <stdint.h> + #include "smbuslib.h" void smbus_common_init(void) diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 7bdaada..f6a211b 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -2,17 +2,22 @@ #define __SIMPLE_DEVICE__ +#include <assert.h> +#include <commonlib/bsd/helpers.h> #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_type.h> #include <device/spi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> #include <soc/pci_devs.h> #include <spi-generic.h> +#include <types.h> const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 86ca4e1..97344cd 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -2,6 +2,7 @@ #include <arch/romstage.h> #include <cbmem.h> +#include <commonlib/bsd/helpers.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/common/block/usb4/pcie.c b/src/soc/intel/common/block/usb4/pcie.c index 81496ce..85292e2 100644 --- a/src/soc/intel/common/block/usb4/pcie.c +++ b/src/soc/intel/common/block/usb4/pcie.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_device.h> #include <acpi/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/path.h> #include <string.h> + #include "chip.h" #define PCI_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 3300768..495996e 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -5,6 +5,7 @@ #include <device/pci_ids.h> #include <intelblocks/xdci.h> #include <security/vboot/vboot_common.h> +#include <stdbool.h> __weak void soc_xdci_init(struct device *dev) { /* no-op */ } diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c index e89fe4c..bf265515 100644 --- a/src/soc/intel/common/fsp_reset.c +++ b/src/soc/intel/common/fsp_reset.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <fsp/util.h> #include <soc/intel/common/reset.h> +#include <stdint.h> void chipset_handle_reset(uint32_t status) { diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 41ecac1..dceb031 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <delay.h> #include <device/azalia_device.h> #include <device/mmio.h> -#include <delay.h> +#include <stdint.h> #include "hda_verb.h" diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index c7da3b3..06a35c7 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -3,8 +3,8 @@ #ifndef _COMMON_SMBIOS_H_ #define _COMMON_SMBIOS_H_ -#include <stdint.h> #include <memory_info.h> +#include <types.h> /* Offset info DIMM_INFO SpdSave for start of serial number */ #define SPD_SAVE_OFFSET_SERIAL 5 diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 690fb5f..c01db66 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -2,9 +2,10 @@ #include <acpi/acpi.h> #include <bootmode.h> +#include <drivers/intel/gma/opregion.h> +#include <stddef.h> #include "vbt.h" -#include <drivers/intel/gma/opregion.h> void *vbt_get(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/68702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Gerrit-Change-Number: 68702 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: treewide: Add 'IWYU pragma: export' comment
by Martin Roth (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Nico Huber, Martin L Roth, Paul Menzel, Angel Pons, Julius Werner, Kyösti Mälkki, Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68332 ) Change subject: treewide: Add 'IWYU pragma: export' comment ...................................................................... Patch Set 11: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68332/comment/19e515ce_4a0fdcda PS11, Line 11: > here: https://review.coreboot. […] Done Patchset: PS11: Awesome! Thanks Elyes. -- To view, visit https://review.coreboot.org/c/coreboot/+/68332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Gerrit-Change-Number: 68332 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 25 Oct 2022 16:25:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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