coreboot-gerrit October 2022

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[S] Change in coreboot[master]: ec/google/wilco/superio: Fix PS2K under Windows
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68463 ) Change subject: ec/google/wilco/superio: Fix PS2K under Windows ...................................................................... ec/google/wilco/superio: Fix PS2K under Windows PS2K device needs to be under PCI0, not LPCB, for Windows to recognize it. Same change was made to ChromeEC previously. Test: Boot Win11 on Drallion, verify built-in keyboard functional. Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/ec/google/wilco/acpi/superio.asl 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl index a779147..b2737c3 100644 --- a/src/ec/google/wilco/acpi/superio.asl +++ b/src/ec/google/wilco/acpi/superio.asl @@ -36,7 +36,10 @@ EndDependentFn () }) } +} +Scope (\_SB.PCI0) +{ Device (PS2K) { Name (_HID, EisaId ("PNP0303")) -- To view, visit https://review.coreboot.org/c/coreboot/+/68463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300 Gerrit-Change-Number: 68463 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Add functions to store/restore uart state in smm
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68567 ) Change subject: soc/intel/xeon_sp: Add functions to store/restore uart state in smm ...................................................................... soc/intel/xeon_sp: Add functions to store/restore uart state in smm When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware initialization that may interfere with OS. Here we store the state before console initialization and restore state before SMM exit. Tested=On not public yet system, after exiting smm, uart console can still work well. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/soc/intel/xeon_sp/smihandler.c 1 file changed, 63 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/smihandler.c b/src/soc/intel/xeon_sp/smihandler.c index 1c04b95..d644447 100644 --- a/src/soc/intel/xeon_sp/smihandler.c +++ b/src/soc/intel/xeon_sp/smihandler.c @@ -1,12 +1,55 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <console/console.h> +#include <console/uart.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <drivers/uart/uart8250reg.h> #include <intelblocks/smihandler.h> #include <soc/pci_devs.h> #include <soc/pm.h> +struct uart8250_state { + uint8_t IER, IIR, MCR, LCR, DLL, DLM; +}; + +static struct uart8250_state s_uart8250_state; + +static void uart8250_store(unsigned int base_port) +{ + /* Save previous state for restoring later. */ + s_uart8250_state.IER = inb(base_port + UART8250_IER); + s_uart8250_state.IIR = inb(base_port + UART8250_FCR); + s_uart8250_state.MCR = inb(base_port + UART8250_MCR); + s_uart8250_state.LCR = inb(base_port + UART8250_LCR); + s_uart8250_state.DLL = inb(base_port + UART8250_DLL); + s_uart8250_state.DLM = inb(base_port + UART8250_DLM); +} + +void smm_soc_early_init(void) +{ + if (CONFIG(DRIVERS_UART_8250IO) && CONFIG(DEBUG_SMI)) + uart8250_store(uart_platform_base(CONFIG_UART_FOR_CONSOLE)); +} + +static void uart8250_restore(unsigned int base_port) +{ + outb(s_uart8250_state.DLL, base_port + UART8250_DLL); + outb(s_uart8250_state.DLM, base_port + UART8250_DLM); + outb(s_uart8250_state.MCR, base_port + UART8250_MCR); + outb(s_uart8250_state.LCR, base_port + UART8250_LCR); + if ((s_uart8250_state.IIR & UART8250_IIR_FIFO_EN) == UART8250_IIR_FIFO_EN) + outb(UART8250_FCR_FIFO_EN, base_port + UART8250_FCR); + outb(s_uart8250_state.IER, base_port + UART8250_IER); +} + +void smm_soc_exit(void) +{ + if (CONFIG(DRIVERS_UART_8250IO) && CONFIG(DEBUG_SMI)) + uart8250_restore(uart_platform_base(CONFIG_UART_FOR_CONSOLE)); +} + /* * Specific SOC SMI handler during ramstage finalize phase */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Gerrit-Change-Number: 68567 Gerrit-PatchSet: 6 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/drivers/uart: Add definition of FIFO enabled in IIR
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68566 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: src/drivers/uart: Add definition of FIFO enabled in IIR ...................................................................... src/drivers/uart: Add definition of FIFO enabled in IIR Interrupt Identification Register (IIR) is a I/O read-access register. Add definition of FIFO enabled for this register so that we can check whether FIFO is enabled or not. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68566 Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/uart/uart8250reg.h 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, approved diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index 35a6845..c6f23ac 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -24,6 +24,7 @@ #define UART8250_IIR_THRI 0x02 /* Transmitter holding register empty */ #define UART8250_IIR_RDI 0x04 /* Receiver data interrupt */ #define UART8250_IIR_RLSI 0x06 /* Receiver line status interrupt */ +#define UART8250_IIR_FIFO_EN 0xC0 /* FIFO enabled */ #define UART8250_FCR 0x02 #define UART8250_FCR_FIFO_EN BIT(0) /* Fifo enable */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4 Gerrit-Change-Number: 68566 Gerrit-PatchSet: 4 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: payloads/edk2: Add the declaration for OBJCOPY
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68744 ) Change subject: payloads/edk2: Add the declaration for OBJCOPY ...................................................................... payloads/edk2: Add the declaration for OBJCOPY The Shimlayer recipe requires OBJCOPY, so declare it at the top of the Makefile so this recipe works as intended. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I2e04dfe18df6252261836dcdf98f7e8de65287b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68744 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M payloads/external/edk2/Makefile 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index ff1dfbc..27ce4a9 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -8,6 +8,8 @@ export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY))) export PACKAGES_PATH := $(EDK2_PATH) +OBJCOPY = $(GCC_PREFIX)objcopy + ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y) BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc endif -- To view, visit https://review.coreboot.org/c/coreboot/+/68744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e04dfe18df6252261836dcdf98f7e8de65287b5 Gerrit-Change-Number: 68744 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68669 ) Change subject: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock ...................................................................... soc/intel/elkhartlake: Fix incorrect divider for MDIO clock After some measurements it turned out that Elkhart Lake uses a higher CSR clock internally from which the MDIO clock is derived. In order to stay compliant with the specification, the MDIO clock needs to be lower than 2.5 MHz. Therefore, the divider needs to be 102 and not 62. This patch changes the define to match the new divider value and uses this new define at the appropriate place. Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz. Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h M src/soc/intel/elkhartlake/tsn_gbe.c 2 files changed, 26 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h index b1d04cc..cd9f12e 100644 --- a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h +++ b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h @@ -15,7 +15,7 @@ #define TSN_MAC_PHYAD(pa) (pa << 21) /* Physical Layer Address */ #define TSN_MAC_REGAD(rda) (rda << 16) /* Register/Device Address */ #define TSN_MAC_CLK_TRAIL_4 (4 << 12) /* 4 Trailing Clocks */ -#define TSN_MAC_CSR_CLK_DIV_62 (1 << 8) /* 0001: CSR=100-150 MHz; CSR/62 */ +#define TSN_MAC_CSR_CLK_DIV_102 (1 << 10) /* 0100: CSR=150-250 MHz; CSR/102 */ #define TSN_MAC_OP_CMD_WRITE (1 << 2) /* GMII Operation Command Write */ #define TSN_MAC_OP_CMD_READ (3 << 2) /* GMII Operation Command Read */ #define TSN_MAC_GMII_BUSY (1 << 0) /* GMII Busy bit */ diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index 3e08897..2a1468c 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -52,7 +52,7 @@ clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 + | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 | TSN_MAC_OP_CMD_READ | TSN_MAC_GMII_BUSY); /* Wait for MDIO frame transfer to complete before reading MDIO DATA register */ @@ -75,7 +75,7 @@ write16(base + TSN_MAC_MDIO_DATA, data); clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62 + | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 | TSN_MAC_OP_CMD_WRITE | TSN_MAC_GMII_BUSY); /* Wait for MDIO frame transfer to complete before do next */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl1: Disable L1 prefetcher
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68668 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl1: Disable L1 prefetcher ...................................................................... mb/siemens/mc_ehl1: Disable L1 prefetcher The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index bc3c4a0..319a8437 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -132,6 +132,9 @@ .vcc_low_high_us = 50, }" + # Disable L1 prefetcher + register "L1_prefetcher_disable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/68668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Gerrit-Change-Number: 68668 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
by Felix Held (Code Review) 25 Oct '22

25 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68667 ) Change subject: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher ...................................................................... soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher Depending on the real workload that is executed on the system the L1 prefetcher might be too aggressive and will populate the L1 cache ahead with data that is not really needed. In the end, this will result in a higher cache miss rate thus slowing down the real application. This patch provides a devicetree option to disable the L1 prefetcher if needed. This can be requested on mainboard level if needed. Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/cpu.c 2 files changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index d63844f..94a2cdf 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -454,6 +454,9 @@ * 3600, 3733, 4000, 4200, 4267 and 0 for Auto. */ uint16_t max_dram_speed_mts; + + /* Disable L1 prefetcher */ + bool L1_prefetcher_disable; }; typedef struct soc_intel_elkhartlake_config config_t; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index f4baa65..8ba28c0 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -67,6 +67,14 @@ msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); + + /* In some cases it is beneficial for the performance to disable the + L1 prefetcher as on Elkhart Lake it is set up a bit too aggressive. */ + if (conf->L1_prefetcher_disable) { + msr = rdmsr(MSR_PREFETCH_CTL); + msr.lo |= PREFETCH_L1_DISABLE; + wrmsr(MSR_PREFETCH_CTL, msr); + } } /* All CPUs including BSP will run the following function. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Gerrit-Change-Number: 68667 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/mediatek: Add support for input 1P mode of dp_intf
by 9elements QA (Code Review) 25 Oct '22

25 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68485 ) Change subject: soc/mediatek: Add support for input 1P mode of dp_intf ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130645 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130644 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130643 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130642 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130641 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130640 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130639 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130638 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130637 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130636 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130635 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130634 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130633 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130632 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130631 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130630 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba Gerrit-Change-Number: 68485 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 15:03:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT
by Paul Menzel (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68742 ) Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68742/comment/47096e4a_6571e1e4 PS1, Line 9: thermal table config E Why E? -- To view, visit https://review.coreboot.org/c/coreboot/+/68742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Gerrit-Change-Number: 68742 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Isaac Lee <isaaclee(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 15:01:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib/fsp_relocate: Fix Coverity Issues
by Paul Menzel (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Ed Sharma, Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68637 ) Change subject: commonlib/fsp_relocate: Fix Coverity Issues ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68637/comment/56b52a33_a3201bf0 PS2, Line 7: commonlib/fsp_relocate: Fix Coverity Issues For the summary/title it’s not important what tool found an issue. Please look through `git log --grep overity` how to be more specific. https://review.coreboot.org/c/coreboot/+/68637/comment/583dc665_cc021366 PS2, Line 9: Recently committed change 1df1cf9 resulted in some Coverity : reported issues. This change attempts to fix the static : analysis issues reported. The issues were reported as : comments in https://review.coreboot.org/c/coreboot/+/66819 : I have looked at all Coverity fixes before my change using : git log --oneline | grep -i coverity and then detailed : git diffs for all coverity changes. However none of them : had the same coverity errors reported as were reported : for my changes. I do not have the manner to run coverity : on my own to test my changes against coverity tests. : : TESTED= : This code is tested with Intel CooperLake-SP FSP version : 2.2.0.33A for DeltaLake boot Please reflow for 72 characters per line. Patchset: PS2: Welcome to coreboot. Thanks a lot for your contribution. -- To view, visit https://review.coreboot.org/c/coreboot/+/68637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I635c62929e8be9a474a91a62c29c3b5ee9b0ee64 Gerrit-Change-Number: 68637 Gerrit-PatchSet: 2 Gerrit-Owner: Ed Sharma <aeddiesharma(a)fb.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ed Sharma <aeddiesharma(a)fb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 15:00:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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