coreboot-gerrit October 2022

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[S] Change in coreboot[master]: mb/prodrive/hermes: Remove FSP workaround
by Paul Menzel (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Patrick Rudolph, Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68814 ) Change subject: mb/prodrive/hermes: Remove FSP workaround ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68814/comment/a469934d_a2511756 PS1, Line 7: mb/prodrive/hermes: Remove FSP workaround Maybe: > Increase CBFS size to 16 MB after FSP fix https://review.coreboot.org/c/coreboot/+/68814/comment/792e43bc_78f10620 PS1, Line 9: FSP releases Would be nice if you documented the first fixed release. -- To view, visit https://review.coreboot.org/c/coreboot/+/68814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If024a3de808c7d9f62171d75350545bc9fdeb9e0 Gerrit-Change-Number: 68814 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 25 Oct 2022 14:51:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45278 ) Change subject: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps ...................................................................... WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps Use GPIOs mapping defined in APCB GET_SPD_FROM_GPIO to fetch correct SPD block from PSP BIOS table entry type 0x69 (BIOS_SPD_DATA). There is only one APCB now with no SPD data in it. No need for board ID getting method. This will save ROM space consumed by multiple APCB copies in the past. This is a working example of an implementation tested on Dalboz. It does not require patching with APCB_EDIT_TOOL. All SPDs are assembled in one type 0x69 blob and inserted into PSP BIOS directory. BUG=b:127505025 TEST=Dalboz with CABLRV20090300 and test CB and boot loader code BRANCH=Zork Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 42 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45278/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index eb2be50..e83e08d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -198,7 +198,7 @@ # # type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) +PSP_SPD_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/SPD_$(f).bin) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -262,6 +262,12 @@ # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 +# SPD data array blob (with SPDs for all possible memory IDs for this platform) +SPD_BLOB:=$(obj)/SPD_array.bin + +# APCB binary without SPD data +APCB_NO_SPD_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + # Helper function to return a value with given bit set set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ @@ -304,9 +310,8 @@ OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) -OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ - $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ - --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) +OPT_PSP_APCB_FILE=$(call add_opt_prefix, $(APCB_NO_SPD_BLOB), --instance 0 --apcb) +OPT_SPD_BLOB=$(call add_opt_prefix, $(SPD_BLOB), --spd-data-blob) OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) @@ -341,7 +346,8 @@ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_APCB_FILE) \ + $(OPT_SPD_BLOB) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ @@ -383,6 +389,16 @@ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) +# Copy prebuild APCBs if they exist +$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin + cp $< $@ + +$(obj)/SPD_%.bin: $$(SPD_SOURCES_DIR)/%.hex + xxd -r -p $< > $@ + +$(SPD_BLOB): $$(PSP_SPD_FILES) + cat $+ > $@ + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ @@ -418,12 +434,22 @@ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(PSP_VERSTAGE_FILE) \ $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ + $(PSP_APCB_FILE) \ + $(SPD_BLOB) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + echo $(AMDFWTOOL) \ + $(OPT_PSPBTLDR_FILE) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB0_NV_SIZE) \ + $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --output $@ $(AMDFWTOOL) \ $(OPT_PSPBTLDR_FILE) \ $(AMDFW_COMMON_ARGS) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f385068..2192a04 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -215,6 +215,7 @@ printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); + printf("--spd-data-blob Add SPD array\n"); printf("-C | --soc-name <socname> Specify SOC name. Supported names are\n"); printf(" Stoneyridge, Raven, Picasso, Renoir or Lucienne"); printf("-h | --help show this help\n"); @@ -251,6 +252,7 @@ AMD_BIOS_PMUD = 0x65, AMD_BIOS_UCODE = 0x66, AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_SPD_DATA = 0x69, AMD_BIOS_MP2_CFG = 0x6a, AMD_BIOS_PSP_SHARED_MEM = 0x6b, AMD_BIOS_L2_PTR = 0x70, @@ -409,6 +411,7 @@ { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, + { .type = AMD_BIOS_SPD_DATA, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, @@ -1085,6 +1088,7 @@ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, LONGOPT_SPI_MICRON_FLAG = 258, + LONGOPT_SPD_DATA = 259, }; // Unused values: D @@ -1136,6 +1140,7 @@ {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, + {"spd-data-blob", required_argument, 0, LONGOPT_SPD_DATA }, /* Embedded Firmware Structure items*/ {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, @@ -1450,6 +1455,11 @@ instance, optarg); sub = instance = 0; break; + case LONGOPT_SPD_DATA: + /* optional SPD data array outside of APCB */ + register_bdt_data(AMD_BIOS_SPD_DATA, sub, instance, optarg); + sub = instance = 0; + break; case 'Q': /* APOB destination */ register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/45278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Gerrit-Change-Number: 45278 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/prodrive/atlas: Add IBECC Kconfig option
by Paul Menzel (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Christian Walter, Maximilian Brune, Angel Pons, Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68783 ) Change subject: mb/prodrive/atlas: Add IBECC Kconfig option ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68783/comment/748ead3f_5ba55543 PS1, Line 10: indurance testing Is the test currently failing, or is the feature tested? https://review.coreboot.org/c/coreboot/+/68783/comment/45101696_26239992 PS1, Line 10: Code), which is currently needed for indurance testing Please add a dot/period at the end of sentences. -- To view, visit https://review.coreboot.org/c/coreboot/+/68783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Gerrit-Change-Number: 68783 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 14:47:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/intel/alderlake: Add IBECC to Alderlake
by Paul Menzel (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Christian Walter, Tim Wawrzynczak, Maximilian Brune, Angel Pons, Lean Sheng Tan, David Milosevic. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68756 ) Change subject: src/soc/intel/alderlake: Add IBECC to Alderlake ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68756/comment/67b21940_f466ce52 PS5, Line 7: Alderlake Alder Lake, but it’s redundant as it’s in the prefix. https://review.coreboot.org/c/coreboot/+/68756/comment/1e483e4a_f8224da9 PS5, Line 10: Board board? https://review.coreboot.org/c/coreboot/+/68756/comment/9355f93e_ea9181a7 PS5, Line 11: Please elaborate. Is the FSP doing that? Please add how and with what memory modules you tested this. Patchset: PS5: Should something be logged, when this is enabled? -- To view, visit https://review.coreboot.org/c/coreboot/+/68756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Gerrit-Change-Number: 68756 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 14:47:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso/Kconfig: turn on GOP
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Nikolai Vyssotski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49868 ) Change subject: soc/amd/picasso/Kconfig: turn on GOP ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fb8c36174ef7615211a8efddbd4c9fb5d374fd3 Gerrit-Change-Number: 49868 Gerrit-PatchSet: 15 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: mb/google/brya: Create marasov variant
by Paul Menzel (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Frank Chu, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68575 ) Change subject: mb/google/brya: Create marasov variant ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68575/comment/970fe1a2_ce2316ac PS3, Line 2: FrankChu Frank Chu git commit --amend --author="Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>" https://review.coreboot.org/c/coreboot/+/68575/comment/ac2a4f11_a394b9ef PS3, Line 12: (Auto-Generated by create_coreboot_variant.sh version 4.5.0). Please move the . inside, and fix the script. -- To view, visit https://review.coreboot.org/c/coreboot/+/68575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2e30c203ee0dfa6c887a707e9b5074ce89f57ac Gerrit-Change-Number: 68575 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 25 Oct 2022 14:45:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard/amd/chausie: Don't use APCB_FT6_Updatable
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68802 ) Change subject: mainboard/amd/chausie: Don't use APCB_FT6_Updatable ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Does the APCB in 3rdparty/blobs need to be renamed, or is this only for site-local work? It should be renamed or removed. This name implies that we have "Updateable" (RW) APCB binary which s not the case. We only have one APCB binary which is used for both default (0x60) and recovery (0x68) APCBs. -- To view, visit https://review.coreboot.org/c/coreboot/+/68802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c Gerrit-Change-Number: 68802 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 14:44:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68801 ) Change subject: src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68801/comment/286b2933_f405c8bc PS2, Line 7: site-local: Enable override of MAINBOARD_BLOBS_DIR > nit: this is soc/amd/mendocino more than site-local Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23 Gerrit-Change-Number: 68801 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Oct 2022 14:34:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Nikolai Vyssotski, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68801 to look at the new patch set (#3). Change subject: src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR ...................................................................... src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR When using site-local we need to have ability to override MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in site-local). site-local Makefiles.inc should be pulled in first (different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten. Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/mendocino/Makefile.inc 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68801/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23 Gerrit-Change-Number: 68801 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot
by Venkat Thogaru (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Shelley Chen, Taniya Das, Julius Werner, Sudheer Amrabadi. Venkat Thogaru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68384 ) Change subject: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot ...................................................................... Patch Set 6: (3 comments) File src/soc/qualcomm/sc7280/socinfo.c: https://review.coreboot.org/c/coreboot/+/68384/comment/af723466_8f002a97 PS4, Line 57: return false; > I would consider putting a die() or at least an assert(0) at the end of these functions because it s […] Done. Update in latest patch 6 https://review.coreboot.org/c/coreboot/+/68384/comment/df7afee2_b1d79858 PS4, Line 67: printk(BIOS_INFO, "jtagid = %x\n", jtagid); > We already print the SKU ID that is constructed from this, we don't need to spam the log with so man […] Done https://review.coreboot.org/c/coreboot/+/68384/comment/cd38b0aa_e9b4bbd4 PS4, Line 70: printk(BIOS_INFO, "Pro_support: %d\n", chipinfolut[i].pro); > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Gerrit-Change-Number: 68384 Gerrit-PatchSet: 6 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Tue, 25 Oct 2022 14:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit October 2022