coreboot-gerrit October 2022

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[M] Change in coreboot[master]: coreboot_tables: Drop uart PCI addr
by Felix Held (Code Review) 26 Oct '22

26 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68767 ) Change subject: coreboot_tables: Drop uart PCI addr ...................................................................... coreboot_tables: Drop uart PCI addr Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Bill XIE <persmule(a)hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M configs/config.intel_harcuvar M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/uart/Kconfig M src/drivers/uart/pl011.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/lib/coreboot_table.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/intel/quark/Kconfig M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/uart.c M src/soc/ti/am335x/uart.c M tests/lib/coreboot_table-test.c 19 files changed, 20 insertions(+), 52 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, but someone else must approve Bill XIE: Looks good to me, but someone else must approve Hung-Te Lin: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/configs/config.intel_harcuvar b/configs/config.intel_harcuvar index 5c7de12..3476817 100644 --- a/configs/config.intel_harcuvar +++ b/configs/config.intel_harcuvar @@ -4,7 +4,6 @@ CONFIG_BOARD_INTEL_HARCUVAR=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_ENABLE_HSUART=y -CONFIG_UART_PCI_ADDR=0x8000d000 #Sample settings for Denverton-NS FSP. #CONFIG_ADD_FSP_BINARIES=y diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index a8fd5cd..5f6a223 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -191,14 +191,6 @@ * decisions as to which dividers to select and their values * to eventually arrive at the desired console baud-rate. */ u32 input_hertz; - - /* UART PCI address: bus, device, function - * 1 << 31 - Valid bit, PCI UART in use - * Bus << 20 - * Device << 15 - * Function << 12 - */ - u32 uart_pci_addr; }; struct cb_console { diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 3f7ff2d..6b5eb59 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -197,14 +197,6 @@ * decisions as to which dividers to select and their values * to eventually arrive at the desired console baud-rate. */ uint32_t input_hertz; - - /* UART PCI address: bus, device, function - * 1 << 31 - Valid bit, PCI UART in use - * Bus << 20 - * Device << 15 - * Function << 12 - */ - uint32_t uart_pci_addr; }; struct lb_console { diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index beba401..a2a7f9f 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -75,14 +75,3 @@ default n help Use uart_platform_refclk to specify the input clock value. - -config UART_PCI_ADDR - hex "UART's PCI bus, device, function address" - default 0x0 - help - Specify zero if the UART is connected to another bus type. - For PCI based UARTs, build the value as: - * 1 << 31 - Valid bit, PCI UART in use - * Bus << 20 - * Device << 15 - * Function << 12 diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 0a73d82..3653262 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -43,7 +43,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index aa8c969..79df37c 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -114,7 +114,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 1834095..79e786b 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -146,7 +146,6 @@ else serial.regwidth = sizeof(uint8_t); serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 2a7ccc5..4df7039 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -109,7 +109,6 @@ serial->baud = new_serial->baud; serial->regwidth = new_serial->regwidth; serial->input_hertz = new_serial->input_hertz; - serial->uart_pci_addr = new_serial->uart_pci_addr; } void lb_add_console(uint16_t consoletype, void *data) diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 4b1bf32..a2f9116 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -37,7 +37,6 @@ serial.baud = 115200; serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2ecdd37..9783c1d 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -63,14 +63,6 @@ default 3 depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 -# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12 -# Valid bit, PCI UART in use: 1 << 31 -config UART_PCI_ADDR - hex - default 0x800a1000 if ENABLE_BUILTIN_HSUART0 - default 0x800a5000 if ENABLE_BUILTIN_HSUART1 - depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 - ##### # Debug support # The following options provide debug support for the Quark coreboot diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index ba3c71a..11c3452 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -167,7 +167,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = UART_HZ; - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index aba8dd9..77d6de2 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -122,7 +122,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index 98c3d4c..b2cdf67 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -109,7 +109,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 9c50611..c04a773 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -265,7 +265,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 97f9e76..007a980 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -266,7 +266,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 1; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index ef03c04..7943651 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -140,7 +140,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 16a4b11..1268183 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -131,7 +131,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 4; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = 0; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index e3648a9..136d785 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -178,7 +178,6 @@ serial.baud = get_uart_baudrate(); serial.regwidth = 2; serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index 20438ef..5257552 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -127,7 +127,6 @@ serial.baud = 115200; serial.regwidth = 1; serial.input_hertz = 115200 * 16; - serial.uart_pci_addr = 0x0; lb_add_serial(&serial, header); assert_int_equal(1, header->table_entries); @@ -244,7 +243,6 @@ serial.baud = 115200; serial.regwidth = 1; serial.input_hertz = 115200 * 16; - serial.uart_pci_addr = 0x0; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); @@ -419,7 +417,6 @@ assert_int_equal(115200, serial->baud); assert_int_equal(1, serial->regwidth); assert_int_equal(115200 * 16, serial->input_hertz); - assert_int_equal(0x0, serial->uart_pci_addr); break; case LB_TAG_CONSOLE: assert_int_equal(sizeof(struct lb_console), record->size); -- To view, visit https://review.coreboot.org/c/coreboot/+/68767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Gerrit-Change-Number: 68767 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
by Felix Held (Code Review) 26 Oct '22

26 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68626 ) Change subject: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE ...................................................................... mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as kano is using a converged firmware image. BUG=b:253337338 BRANCH=firmware-brya-14505.B TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", disable hardware write protect and software write protect, flash and boot kano in end-of-manufacturing mode to kernel. Cq-Depend: chrome-internal:5046060, chromium:3967356 Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68626 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 9992eea..8c5af45 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -75,6 +75,7 @@ select SOC_INTEL_COMMON_BLOCK_IPU select CHROMEOS_WIFI_SAR if CHROMEOS select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" -- To view, visit https://review.coreboot.org/c/coreboot/+/68626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01 Gerrit-Change-Number: 68626 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ofer Fried <oferfried(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/prodrive/atlas: Disable S3
by Felix Held (Code Review) 26 Oct '22

26 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68591 ) Change subject: mb/prodrive/atlas: Disable S3 ...................................................................... mb/prodrive/atlas: Disable S3 The Atlas board has currently the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/prodrive/atlas/Kconfig 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index ce9aeab..f986a2d 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -4,7 +4,6 @@ select INTEL_LPSS_UART_FOR_CONSOLE select EC_ACPI select FSP_TYPE_IOT - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_TPM2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Gerrit-Change-Number: 68591 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` config
by Felix Held (Code Review) 26 Oct '22

26 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68771 ) Change subject: mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` config ...................................................................... mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` config This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake SoC to Rex mainboard to maintain the symmetry with previous generation ChromeOS devices (Brya and Volteer). BUG=none TEST=Able to build and boot to Google/Rex with USB4 functionality remaining intact. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/Kconfig M src/soc/intel/meteorlake/Kconfig 2 files changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index b56fd58..ebdc2aa 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -4,6 +4,7 @@ select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_WIFI_GENERIC select DRIVERS_INTEL_MIPI_CAMERA diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 9ef58aa..b8e4052 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -17,7 +17,6 @@ select CPU_SUPPORTS_PM_TIMER_EMULATION select DEFAULT_X2APIC_LATE_WORKAROUND select DISPLAY_FSP_VERSION_INFO - select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZ4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Gerrit-Change-Number: 68771 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Add Raptor Lake device IDs
by 9elements QA (Code Review) 26 Oct '22

26 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68565 ) Change subject: soc/intel/alderlake: Add Raptor Lake device IDs ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 3 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130941 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/130940 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/130939 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/130938 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/130937 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130936 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/130935 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/130934 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/130933 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/130932 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/130931 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/130930 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/130929 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/130928 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/130927 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/130926 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Gerrit-Change-Number: 68565 Gerrit-PatchSet: 8 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 13:56:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generation
by Fred Reitberger (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Nien, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68850 ) Change subject: mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6 Gerrit-Change-Number: 68850 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 13:56:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] security/tpm: add TPM log format as per 1.2 spec
by Krystian Hebel (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Sergii Dmytruk. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68747 ) Change subject: [WIP] security/tpm: add TPM log format as per 1.2 spec ...................................................................... Patch Set 2: (6 comments) File src/security/tpm/tpm12_log_serialized.h: https://review.coreboot.org/c/coreboot/+/68747/comment/bf690000_1122c882 PS2, Line 11: TCPA_DIGEST_MAX_LENGTH `TCPA_DIGEST_LENGTH`, there can be no other. https://review.coreboot.org/c/coreboot/+/68747/comment/56194302_45edbd97 PS2, Line 13: #define TCPA_PCR_HASH_LEN 10 What is this for? https://review.coreboot.org/c/coreboot/+/68747/comment/27f1d3e2_93581649 PS2, Line 22: char name[TCPA_PCR_HASH_NAME]; Specification doesn't precise that this is a name, just data. Smaller measured blocks may even be copied here, e.g. `ascii_bios_measurements` for my PC with vendor firmware looks like this: ``` 5 50d327b20ea5f890635a11d8fff2dffbeaa867bb 80000002 [] 5 35c5f66a7073aac2392cf3f71e0e8ddb9569298b 80000002 [] 0 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 1 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 2 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 3 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 4 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 5 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 6 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 7 d9be6524a5f5047db5866813acf3277892a7a30a 04 [��] 5 b6ae9742d3936a4291cfed8df775bc4657e368c0 80000007 [] ``` For better compatibility we should use `uint8_t`. Also, this field should have variable length. https://review.coreboot.org/c/coreboot/+/68747/comment/938e12c3_e17e5a9c PS2, Line 43: uint16_t max_entries; Since fields are not fixed size (in general), instead of `{max,num}_entries` it would be better to keep full size in bytes and offset at which next entry should be added. `tcpa_cbmem_init()` would have to be changed accordingly, as well as code for adding new entries. File src/security/tpm/tspi.h: https://review.coreboot.org/c/coreboot/+/68747/comment/36dd7481_429bb5be PS2, Line 13: #include "tpm12_log_serialized.h" May be worth moving to `commonlib` File src/security/tpm/tspi/log-tpm12.c: https://review.coreboot.org/c/coreboot/+/68747/comment/04115d44_4106ca19 PS2, Line 5: then `than` -- To view, visit https://review.coreboot.org/c/coreboot/+/68747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Gerrit-Change-Number: 68747 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 13:51:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mandolin: introduce mb_get_fch_irq_mapping
by Fred Reitberger (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Glenesk, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68847 ) Change subject: mb/amd/mandolin: introduce mb_get_fch_irq_mapping ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c39ea9de5ebbf70d2c5a87bfdfe270796548c5c Gerrit-Change-Number: 68847 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 13:50:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Update Crota's ELAN touchscreen delay to 150 ms
by Paz Zcharya (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Subrata Banik, Terry Chen, Tim Wawrzynczak, Nick Vaccaro, Franklin Lin. Paz Zcharya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68868 ) Change subject: mb/google/brya: Update Crota's ELAN touchscreen delay to 150 ms ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/variants/crota/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68868/comment/c5bf41cb_1eef071b PS6, Line 225: 150 > do we even need 150ms, on Rex, the reset delay with 20ms is meeting the spec. Spec requires 150 ms minimum delay in between pulling RESET high and sending the first i2c commands. However, in practice, the device (I assume OS) doesn't send commands until about ~2 seconds after the power-on sequence (measured with scope by ELAN). So the short answer is that we can have 0 delay as long as things don't change. However, if all of a sudden OS' flow changes and we power-on the device late / send commands early (unlikely), things might break. -- To view, visit https://review.coreboot.org/c/coreboot/+/68868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17e1f7d419637f6dff4049484ce1836ad98017ea Gerrit-Change-Number: 68868 Gerrit-PatchSet: 6 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Franklin Lin <franklin_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rajat Jain <rajatja(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Franklin Lin <franklin_lin(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 13:44:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd: commonize generation of the PIC/APIC mapping tables
by Fred Reitberger (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68853 ) Change subject: soc/amd: commonize generation of the PIC/APIC mapping tables ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Gerrit-Change-Number: 68853 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 13:41:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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