coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: payloads: Make PAYLOAD_NONE a bool outside of the choice
by Matt DeVillier (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Martin L Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68595 ) Change subject: payloads: Make PAYLOAD_NONE a bool outside of the choice ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I932c65630261a5b39809abf4dfbda5bf932c6684 Gerrit-Change-Number: 68595 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 15:11:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake/hsphy.c: Handle case with DMA protection
by Michał Żygowski (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68556 ) Change subject: soc/intel/alderlake/hsphy.c: Handle case with DMA protection ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Now it work, bug in patch CB:68449 -- To view, visit https://review.coreboot.org/c/coreboot/+/68556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Gerrit-Change-Number: 68556 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 15:07:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Expand cbmem console buffer
by Martin Roth (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Bao Zheng, Jason Nien, Paul Menzel, Zheng Bao. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68293 ) Change subject: mb/google/skyrim: Expand cbmem console buffer ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79205f31b4cc3276c1c213a171a6bf7e18d73a1c Gerrit-Change-Number: 68293 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 26 Oct 2022 15:03:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL
by Subrata Banik (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Tim Wawrzynczak, Nick Vaccaro, Ivy Jian, Eric Lai. Hello Tarun Tuli, Kapil Porwal, Tim Wawrzynczak, Nick Vaccaro, Ivy Jian, Nick Vaccaro, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68901 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL ...................................................................... soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Additionally, no performance degradation is observed while running benchmarks. Refer to Intel Technical White Paper number:751003 for more details. BUG=b:211770003 TEST=Able to boot to ChromeOS with all cores are enabled. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68901/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Gerrit-Change-Number: 68901 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: oc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL
by Subrata Banik (Code Review) 26 Oct '22

26 Oct '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68901 ) Change subject: oc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL ...................................................................... oc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Additionally, no performance degradation is observed while running benchmarks. Refer to Intel Technical White Paper number:751003 for more details. BUG=b:211770003 TEST=Able to boot to ChromeOS with all cores are enabled. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/68901/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 92a8c06..4fe9984 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -7,6 +7,7 @@ config SOC_INTEL_RAPTORLAKE bool + select X86_INIT_NEED_1_SIPI help Intel Raptorlake support. Mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. -- To view, visit https://review.coreboot.org/c/coreboot/+/68901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Gerrit-Change-Number: 68901 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/alderlake/hsphy.c: Handle case with DMA protection
by Michał Żygowski (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68556 to look at the new patch set (#6). Change subject: soc/intel/alderlake/hsphy.c: Handle case with DMA protection ...................................................................... soc/intel/alderlake/hsphy.c: Handle case with DMA protection The HSPHY firmware must be downloaded to DMA-allowed host address space. Check for DMA buffer presence and use it as the buffer for HSPHY firmware to be downloaded from CSME. TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4 with DMA protection enabled. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d --- M src/soc/intel/alderlake/hsphy.c 1 file changed, 48 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/68556/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Gerrit-Change-Number: 68556 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: intelblocks/vtd: Add VT-d block with DMA protection API
by Michał Żygowski (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Michał Żygowski, Angel Pons. Hello build bot (Jenkins), Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68449 to look at the new patch set (#7). Change subject: intelblocks/vtd: Add VT-d block with DMA protection API ...................................................................... intelblocks/vtd: Add VT-d block with DMA protection API Add new common block with VT-d/IOMMU support. The patch adds an option to enable DMA protection with PMR. However the payload and OS must support VT-d in order to properly handle I/O devices. TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 --- A src/soc/intel/common/block/include/intelblocks/vtd.h A src/soc/intel/common/block/vtd/Kconfig A src/soc/intel/common/block/vtd/Makefile.inc A src/soc/intel/common/block/vtd/vtd.c 4 files changed, 357 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68449/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/68449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Gerrit-Change-Number: 68449 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Hung-Te Lin (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Shelley Chen, Julius Werner, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68871 ) Change subject: mem_chip_info: Update to new format ...................................................................... Patch Set 2: (2 comments) File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/68871/comment/093e06c2_1c7122ab PS2, Line 68: mem_chip_info should we add some version / size tags, in case if we'll want to change the structure again in the future? for example u8 entry_size, then we can at least know how to find the next entry correctly. https://review.coreboot.org/c/coreboot/+/68871/comment/7f265758_139695f2 PS2, Line 70: uint8_t reserved[3]; should we reserve 7 bytes, for 64-bit alignment? or make the structure declared as __attribute__((packed))? -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 14:53:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Hung-Te Lin (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Shelley Chen, Julius Werner, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68871 ) Change subject: mem_chip_info: Update to new format ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I think at least the corsola is using this feature and has been branched. Please add BRANCH=corsola -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 14:48:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: lib/coreboot_table: Simplify API to set up lb_serial
by Arthur Heymans (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Hung-Te Lin, Julius Werner, ron minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68768 ) Change subject: lib/coreboot_table: Simplify API to set up lb_serial ...................................................................... Patch Set 7: (1 comment) File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/68768/comment/fa1740fd_fb76ff15 PS7, Line 102: struct lb_serial new_serial = get_lb_serial(); : /* Use the base address as a proxy for an invalid struct */ : if (new_serial.baseaddr == 0) : return; : : serial = (struct lb_serial *)lb_new_record(header); : memcpy(serial, &new_serial, sizeof(*serial)); : serial->tag = LB_TAG_SERIAL; : serial->size = sizeof(*serial); : if (serial->type == LB_SERIAL_TYPE_IO_MAPPED) : lb_add_console(LB_TAG_CONSOLE_SERIAL8250, header); : else : lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, header); > It's true we can return a struct, but the implementation above is > - using a hint baseaddr=0 implies invalid > - assuming the get_lb_serial will only fill partial data > - overwriting the size > > If we're going to change the APIs, I'd rather redefine it as: > int get_lb_serial(struct lb_serial *serial) { > serial->type = ... > return 0; > } > > And then you can do here: > > struct lb_serial new_serial = {0}; > new_serial.tag = LB_TAG_SERIAL; > new_serial.size = sizeof(new_serial); > if (!get_lb_serial(&new_serial)) > return; > // allocate the new record, copy serial etc Nice suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/68768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Gerrit-Change-Number: 68768 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 14:46:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit October 2022