coreboot-gerrit October 2022

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[M] Change in coreboot[master]: soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto Engine
by Karthik Ramasubramanian (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68184 ) Change subject: soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto Engine ...................................................................... Patch Set 10: (1 comment) File src/soc/amd/common/psp_verstage/vboot_crypto.c: https://review.coreboot.org/c/coreboot/+/68184/comment/ca739dff_cadc1757 PS10, Line 98: CONFIG_VBOOT_HASH_BLOCK_SIZE > Hrmm, how large is this? Will this overflow the stack? My testing indicated it should not. Earlier when we verify the entire FW body, vboot used the same amount of memory from the stack - https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he… It is currently at 36 KB - configured on a per-SoC basis. -- To view, visit https://review.coreboot.org/c/coreboot/+/68184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9bc9e786f302e7938969c8093d5405b5a85b711 Gerrit-Change-Number: 68184 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 15:57:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/amdfwtool: Add build rules for amdfwread
by Raul Rangel (Code Review) 26 Oct '22

26 Oct '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66939 ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/amdfwtool: Add build rules for amdfwread ...................................................................... util/amdfwtool: Add build rules for amdfwread Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.inc M src/soc/amd/common/Makefile.inc M util/amdfwtool/Makefile.inc 3 files changed, 30 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index 0ed205f..563a2bc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -600,6 +600,7 @@ IFDTOOL:=$(objutil)/ifdtool/ifdtool AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool +AMDFWREAD:=$(objutil)/amdfwtool/amdfwread APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py @@ -701,7 +702,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) ########################################################################### # Common recipes for all stages diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index a935565..75b1142 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -14,4 +14,8 @@ amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin) +ifeq ($(CONFIG_VBOOT_GSCVD),y) +build_complete:: $(AMDFWREAD) +endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) + endif diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index b61f02c..b9c3ced 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -1,6 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause amdfwtoolobj = amdfwtool.o data_parse.o +amdfwreadobj = amdfwread.o AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror AMDFWTOOLCFLAGS += -I $(top)/src/commonlib/bsd/include @@ -16,3 +17,7 @@ $(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) printf " AMDFWTOOL\n" $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) $(LDFLAGS) -o $@ + +$(objutil)/amdfwtool/amdfwread: $(addprefix $(objutil)/amdfwtool/,$(amdfwreadobj)) + printf " AMDFWREAD\n" + $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwreadobj)) $(LDFLAGS) -o $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/66939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Gerrit-Change-Number: 66939 Gerrit-PatchSet: 13 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: util/amdfwtool/amdfwread: List AMDFW RO binary entries
by Raul Rangel (Code Review) 26 Oct '22

26 Oct '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66761 ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/amdfwtool/amdfwread: List AMDFW RO binary entries ...................................................................... util/amdfwtool/amdfwread: List AMDFW RO binary entries Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories and list the entries present in them. Accommodate both recovery A/B layout and normal layout. This is required to identify the location and size of each entries in the finally built amdfw.rom. This in turn can be used to perform any platform specific verification on the relevant components. BUG=None TEST=Build and list the contents of AMDFW binary. /usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin Table: FW Offset Size PSPL1: Dir 0x00d97000 +-->PSPL1: 0x48 0x00d98000 0x00001000 +-->PSPL2: Dir 0x00c30000 +-->PSPL2: 0x00 0x00c31000 0x00000440 +-->PSPL2: 0x01 0x00c31500 0x00007580 +-->PSPL2: 0x02 0x00c38b00 0x00019470 +-->PSPL2: 0x08 0x00c52000 0x0001f560 +-->PSPL2: 0x09 0x00c71600 0x00000440 +-->PSPL2: 0x0b 0x430000041(Soft-fuse) +-->PSPL2: 0x0c 0x00c71b00 0x00023100 +-->PSPL2: 0x12 0x00c94c00 0x00015890 +-->PSPL2: 0x13 0x00caa500 0x000021c0 +-->PSPL2: 0x20 0x00cac700 0x00000640 +-->PSPL2: 0x21 0x00cace00 0x00000030 +-->PSPL2: 0x22 0x00cad000 0x00001000 +-->PSPL2: 0x24 0x00cae000 0x00003b60 +-->PSPL2: 0x28 0x00cb1c00 0x00022890 +-->PSPL2: 0x2d 0x00cd4500 0x00003100 +-->PSPL2: 0x30 0x00cd7600 0x0006b550 +-->PSPL2: 0x3a 0x00d42c00 0x000006d0 +-->PSPL2: 0x3c 0x00d43300 0x000018c0 +-->PSPL2: 0x44 0x00d44c00 0x00006610 +-->PSPL2: 0x45 0x00d4b300 0x00001c70 +-->PSPL2: 0x50 0x00d4d000 0x00001a00 +-->PSPL2: 0x51 0x00d4ea00 0x00001020 +-->PSPL2: 0x52 0x00d4fb00 0x00010180 +-->PSPL2: 0x55 0x00d5fd00 0x00000600 +-->PSPL2: 0x5a 0x00d60300 0x00000570 +-->PSPL2: 0x5c 0x00d60900 0x00000b20 +-->PSPL2: 0x71 0x00d61500 0x00024710 +-->PSPL2: 0x73 0x00d85d00 0x00010640 +-->PSPL2: 0x8d 0x00d96400 0x00000030 +-->PSPL2: 0x49 0x00d99000 0x00001000 +-->BIOSL2: Dir 0x00d99000 +-->BIOSL2: 0x60 0x00d9a000 0x00009924 +-->BIOSL2: 0x68 0x00da4000 0x00009924 +-->BIOSL2: 0x61 0x2001000(DRAM-Address) +-->BIOSL2: 0x62 0x00dada00 0x00010000 +-->BIOSL2: 0x63 0x00000000 0x0001e000 +-->BIOSL2: 0x64 0x00db4200 0x00006310 +-->BIOSL2: 0x65 0x00dba600 0x000004e0 +-->BIOSL2: 0x64 0x00dbab00 0x00006180 +-->BIOSL2: 0x65 0x00dc0d00 0x00000250 +-->BIOSL2: 0x6b 0x201f000(DRAM-Address) +-->PSPL1: 0x4a 0x00d98000 0x00001000 Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwread.c 1 file changed, 291 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index a65fb26..711b158 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -4,6 +4,7 @@ #include <stdio.h> #include <stdint.h> #include <stdlib.h> +#include <string.h> #include <unistd.h> #include "amdfwtool.h" @@ -116,6 +117,36 @@ return read_header(fw, offset & FILE_REL_MASK, table, sizeof(*table)); } +static int read_bios_directory(FILE *fw, uint32_t offset, uint32_t expected_cookie, + bios_directory_hdr *header, bios_directory_entry **entries, + size_t *num_entries) +{ + offset &= FILE_REL_MASK; + + if (read_header(fw, offset, header, sizeof(bios_directory_hdr))) { + ERR("Failed to read BIOS header\n"); + return 1; + } + + /* Ensure that we have a BIOS directory */ + if (header->cookie != expected_cookie) { + ERR("Invalid BIOS header cookie value found: 0x%x, expected: 0x%x\n", + header->cookie, expected_cookie); + return 1; + } + + /* Read the entries */ + *num_entries = header->num_entries; + *entries = malloc(sizeof(bios_directory_entry) * header->num_entries); + if (fread(*entries, sizeof(bios_directory_entry), header->num_entries, fw) + != header->num_entries) { + ERR("Failed to read %d BIOS entries\n", header->num_entries); + return 1; + } + + return 0; +} + static int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header) { psp_directory_entry *current_entries = NULL; @@ -203,9 +234,189 @@ return 1; } +#define MAX_NUM_LEVELS 10 +#define MAX_INDENT_PER_LEVEL 4 +#define MAX_INDENTATION_LEN (MAX_NUM_LEVELS * MAX_INDENT_PER_LEVEL + 1) +static void do_indentation_string(char *dest, uint8_t level) +{ + for (uint8_t i = 0; i < level && i < MAX_NUM_LEVELS; i++) + strcat(dest, " "); + strcat(dest, "+-->"); +} + +static int amdfw_bios_dir_walk(FILE *fw, uint32_t bios_offset, uint32_t cookie, uint8_t level) +{ + bios_directory_entry *current_entries = NULL; + size_t num_current_entries = 0; + bios_directory_hdr header; + uint32_t l2_dir_offset = 0; + char indent[MAX_INDENTATION_LEN] = {0}; + + if (read_bios_directory(fw, bios_offset, cookie, &header, + &current_entries, &num_current_entries) != 0) + return 1; + + do_indentation_string(indent, level); + for (size_t i = 0; i < num_current_entries; i++) { + uint32_t type = current_entries[i].type; + uint64_t mode = current_entries[i].address_mode; + uint64_t addr = current_entries[i].source; + + if (type == AMD_BIOS_APOB || type == AMD_BIOS_PSP_SHARED_MEM) + printf("%sBIOS%s: 0x%02x 0x%lx(DRAM-Address)\n", + indent, cookie == BHD_COOKIE ? "L1" : "L2", + type, current_entries[i].dest); + else if (type == AMD_BIOS_APOB_NV) + printf("%sBIOS%s: 0x%02x 0x%08lx 0x%08x\n", + indent, cookie == BHD_COOKIE ? "L1" : "L2", + type, relative_offset(bios_offset, addr, AMD_ADDR_PHYSICAL), + current_entries[i].size); + else + printf("%sBIOS%s: 0x%02x 0x%08lx 0x%08x\n", + indent, cookie == BHD_COOKIE ? "L1" : "L2", + type, relative_offset(bios_offset, addr, mode), + current_entries[i].size); + + if (type == AMD_BIOS_L2_PTR) { + /* There's a second level BIOS directory to read */ + if (l2_dir_offset != 0) { + ERR("Duplicate BIOS L2 Entry, prior offset: %08x\n", + l2_dir_offset); + free(current_entries); + return 1; + } + + l2_dir_offset = relative_offset(bios_offset, addr, mode); + printf(" %sBIOSL2: Dir 0x%08x\n", indent, l2_dir_offset); + amdfw_bios_dir_walk(fw, l2_dir_offset, BHDL2_COOKIE, level + 2); + } + } + + free(current_entries); + return 0; +} + +static int amdfw_psp_dir_walk(FILE *fw, uint32_t psp_offset, uint32_t cookie, uint8_t level) +{ + psp_directory_entry *current_entries = NULL; + size_t num_current_entries = 0; + psp_directory_header header; + uint32_t l2_dir_offset = 0; + uint32_t bios_dir_offset = 0; + uint32_t ish_dir_offset = 0; + ish_directory_table ish_dir; + char indent[MAX_INDENTATION_LEN] = {0}; + + if (read_psp_directory(fw, psp_offset, cookie, &header, + &current_entries, &num_current_entries) != 0) + return 1; + + do_indentation_string(indent, level); + for (size_t i = 0; i < num_current_entries; i++) { + uint32_t type = current_entries[i].type; + uint64_t mode = current_entries[i].address_mode; + uint64_t addr = current_entries[i].addr; + + if (type == AMD_PSP_FUSE_CHAIN) + printf("%sPSP%s: 0x%02x 0x%lx(Soft-fuse)\n", + indent, cookie == PSP_COOKIE ? "L1" : "L2", + type, mode << 62 | addr); + else + printf("%sPSP%s: 0x%02x 0x%08lx 0x%08x\n", + indent, cookie == PSP_COOKIE ? "L1" : "L2", + type, relative_offset(psp_offset, addr, mode), + current_entries[i].size); + + switch (type) { + case AMD_FW_L2_PTR: + /* There's a second level PSP directory to read */ + if (l2_dir_offset != 0) { + ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", + l2_dir_offset); + free(current_entries); + return 1; + } + + l2_dir_offset = relative_offset(psp_offset, addr, mode); + printf(" %sPSPL2: Dir 0x%08x\n", indent, l2_dir_offset); + amdfw_psp_dir_walk(fw, l2_dir_offset, PSPL2_COOKIE, level + 2); + break; + + case AMD_FW_RECOVERYAB_A: + if (l2_dir_offset != 0) { + ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", + l2_dir_offset); + free(current_entries); + return 1; + } + + ish_dir_offset = relative_offset(psp_offset, addr, mode); + if (read_ish_directory(fw, ish_dir_offset, &ish_dir) != 0) { + ERR("Error reading ISH directory\n"); + free(current_entries); + return 1; + } + + l2_dir_offset = ish_dir.pl2_location; + printf(" %sPSPL2: Dir 0x%08x\n", indent, l2_dir_offset); + amdfw_psp_dir_walk(fw, l2_dir_offset, PSPL2_COOKIE, level + 2); + break; + + case AMD_FW_BIOS_TABLE: + bios_dir_offset = relative_offset(psp_offset, addr, mode); + printf(" %sBIOSL2: Dir 0x%08x\n", indent, bios_dir_offset); + amdfw_bios_dir_walk(fw, bios_dir_offset, BHDL2_COOKIE, level + 2); + break; + + default: + /* No additional processing required, continue to the next entry. */ + break; + } + } + + free(current_entries); + return 0; +} + +static int list_amdfw_psp_dir(FILE *fw, const embedded_firmware *fw_header) +{ + uint32_t psp_offset = 0; + + /* 0xffffffff indicates that the offset is in new_psp_directory */ + if (fw_header->psp_directory != 0xffffffff) + psp_offset = fw_header->psp_directory; + else + psp_offset = fw_header->new_psp_directory; + + printf("PSPL1: Dir 0x%08x\n", psp_offset); + amdfw_psp_dir_walk(fw, psp_offset, PSP_COOKIE, 0); + return 0; +} + +static int list_amdfw_bios_dir(FILE *fw, const embedded_firmware *fw_header) +{ + /* 0xffffffff implies that the SoC uses recovery A/B layout. Only BIOS L2 directory + is present and that too as part of PSP L2 directory. */ + if (fw_header->bios3_entry != 0xffffffff) { + printf("BIOSL1: Dir 0x%08x\n", fw_header->bios3_entry); + amdfw_bios_dir_walk(fw, fw_header->bios3_entry, BHD_COOKIE, 0); + } + return 0; +} + + +static int list_amdfw_ro(FILE *fw, const embedded_firmware *fw_header) +{ + printf("Table: FW Offset Size\n"); + list_amdfw_psp_dir(fw, fw_header); + list_amdfw_bios_dir(fw, fw_header); + return 0; +} + enum { AMDFW_OPT_HELP = 'h', AMDFW_OPT_SOFT_FUSE = 1UL << 0, /* Print Softfuse */ + AMDFW_OPT_RO_LIST = 1UL << 1, /* List entries in AMDFW RO */ }; static char const optstring[] = {AMDFW_OPT_HELP}; @@ -213,6 +424,7 @@ static struct option long_options[] = { {"help", no_argument, 0, AMDFW_OPT_HELP}, {"soft-fuse", no_argument, 0, AMDFW_OPT_SOFT_FUSE}, + {"ro-list", no_argument, 0, AMDFW_OPT_RO_LIST}, }; static void print_usage(void) @@ -220,6 +432,7 @@ printf("amdfwread: Examine AMD firmware images\n"); printf("Usage: amdfwread [options] <file>\n"); printf("--soft-fuse Print soft fuse value\n"); + printf("--ro-list List the programs under AMDFW in RO region\n"); } int main(int argc, char **argv) @@ -248,6 +461,7 @@ return 0; case AMDFW_OPT_SOFT_FUSE: + case AMDFW_OPT_RO_LIST: selected_functions |= opt; break; @@ -285,6 +499,13 @@ } } + if (selected_functions & AMDFW_OPT_RO_LIST) { + if (list_amdfw_ro(fw, &fw_header) != 0) { + fclose(fw); + return 1; + } + } + fclose(fw); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/66761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd Gerrit-Change-Number: 66761 Gerrit-PatchSet: 15 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/amdfwtool/amdfwread: Handle recovery A/B layout
by Raul Rangel (Code Review) 26 Oct '22

26 Oct '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66554 ) ( 15 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/amdfwtool/amdfwread: Handle recovery A/B layout ...................................................................... util/amdfwtool/amdfwread: Handle recovery A/B layout Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to handle it. Also add a generic read_header function to read different header types. BUG=None TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to dump the Softfuse entry. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwread.c 1 file changed, 79 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index 1701e20..a65fb26 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -56,14 +56,24 @@ } } -static int read_fw_header(FILE *fw, uint32_t offset, embedded_firmware *fw_header) +static int read_header(FILE *fw, uint32_t offset, void *header, size_t header_size) { if (fseek(fw, offset, SEEK_SET) != 0) { - ERR("Failed to seek to fw header offset 0x%x\n", offset); + ERR("Failed to seek to file offset 0x%x\n", offset); return 1; } - if (fread(fw_header, sizeof(embedded_firmware), 1, fw) != 1) { + if (fread(header, header_size, 1, fw) != 1) { + ERR("Failed to read header at 0x%x\n", offset); + return 1; + } + + return 0; +} + +static int read_fw_header(FILE *fw, uint32_t offset, embedded_firmware *fw_header) +{ + if (read_header(fw, offset, fw_header, sizeof(embedded_firmware))) { ERR("Failed to read fw header at 0x%x\n", offset); return 1; } @@ -77,13 +87,8 @@ { offset &= FILE_REL_MASK; - if (fseek(fw, offset, SEEK_SET) != 0) { - ERR("Failed to seek to PSP header at 0x%x\n", offset); - return 1; - } - - if (fread(header, sizeof(psp_directory_header), 1, fw) != 1) { - ERR("Failed to read PSP header cookie\n"); + if (read_header(fw, offset, header, sizeof(psp_directory_header))) { + ERR("Failed to read PSP header\n"); return 1; } @@ -106,6 +111,11 @@ return 0; } +static int read_ish_directory(FILE *fw, uint32_t offset, ish_directory_table *table) +{ + return read_header(fw, offset & FILE_REL_MASK, table, sizeof(*table)); +} + static int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header) { psp_directory_entry *current_entries = NULL; @@ -125,23 +135,56 @@ while (1) { uint32_t l2_dir_offset = 0; + uint32_t ish_dir_offset; + ish_directory_table ish_dir; for (size_t i = 0; i < num_current_entries; i++) { uint32_t type = current_entries[i].type; uint64_t mode = current_entries[i].address_mode; uint64_t addr = current_entries[i].addr; + uint64_t fuse; - if (type == AMD_PSP_FUSE_CHAIN) { - uint64_t fuse = mode << 62 | addr; + switch (type) { + case AMD_PSP_FUSE_CHAIN: + fuse = mode << 62 | addr; printf("Soft-fuse:0x%lx\n", fuse); + free(current_entries); return 0; - } else if (type == AMD_FW_L2_PTR) { + + case AMD_FW_L2_PTR: /* There's a second level PSP directory to read */ - if (l2_dir_offset != 0) + if (l2_dir_offset != 0) { + ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", + l2_dir_offset); + free(current_entries); return 1; + } l2_dir_offset = relative_offset(psp_offset, addr, mode); + break; + + case AMD_FW_RECOVERYAB_A: + if (l2_dir_offset != 0) { + ERR("Duplicate PSP L2 Entry, prior offset: %08x\n", + l2_dir_offset); + free(current_entries); + return 1; + } + + ish_dir_offset = relative_offset(psp_offset, addr, mode); + if (read_ish_directory(fw, ish_dir_offset, &ish_dir) != 0) { + ERR("Error reading ISH directory\n"); + free(current_entries); + return 1; + } + + l2_dir_offset = ish_dir.pl2_location; + break; + + default: + /* No-op, continue to the next entry. */ + break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/66554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15 Gerrit-Change-Number: 66554 Gerrit-PatchSet: 17 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask
by Raul Rangel (Code Review) 26 Oct '22

26 Oct '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66573 ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask ...................................................................... util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask Optional arguments that involve printing information from the firmware image is mapped to bit fields with bit 31 set. But instead of just setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573 Reviewed-by: Robert Zieba <robertzieba(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwread.c 1 file changed, 32 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Robert Zieba: Looks good to me, but someone else must approve diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index ccb81b3..1701e20 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -162,10 +162,7 @@ enum { AMDFW_OPT_HELP = 'h', - - /* When bit 31 is set, options are a bitfield of info to print from the - firmware image. */ - AMDFW_OPT_SOFT_FUSE = 0xF0000001, + AMDFW_OPT_SOFT_FUSE = 1UL << 0, /* Print Softfuse */ }; static char const optstring[] = {AMDFW_OPT_HELP}; @@ -202,12 +199,18 @@ break; } - if (opt == AMDFW_OPT_HELP) { + switch (opt) { + case AMDFW_OPT_HELP: print_usage(); return 0; - } - selected_functions |= opt; + case AMDFW_OPT_SOFT_FUSE: + selected_functions |= opt; + break; + + default: + break; + } } FILE *fw = fopen(fw_file, "rb"); -- To view, visit https://review.coreboot.org/c/coreboot/+/66573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48 Gerrit-Change-Number: 66573 Gerrit-PatchSet: 16 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/amdfwtool/amdfwread: Update relative_offset function
by Raul Rangel (Code Review) 26 Oct '22

26 Oct '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66572 ) Change subject: util/amdfwtool/amdfwread: Update relative_offset function ...................................................................... util/amdfwtool/amdfwread: Update relative_offset function * AMD_ADDR_PHYSICAL refers to physical address in the memory map * AMD_ADDR_REL_BIOS is relative to the start of the BIOS image * AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS tables Update the relative_offset implementation accordingly. Though AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify the relative_offset implementation so that it can be used for both PSP and BIOS firmware tables. Hence update the relative_offset function signature as well. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M util/amdfwtool/amdfwread.c 1 file changed, 56 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index d6dc1e2..ccb81b3 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -10,6 +10,7 @@ /* An address can be relative to the image/file start but it can also be the address when * the image is mapped at 0xff000000. Used to ensure that we only attempt to read within * the limits of the file. */ +#define SPI_ROM_BASE 0xff000000 #define FILE_REL_MASK 0xffffff #define ERR(...) fprintf(stderr, __VA_ARGS__) @@ -24,28 +25,35 @@ }; /* Converts addresses to be relative to the start of the file */ -static uint64_t relative_offset(const psp_directory_header *header, uint32_t header_offset, - const psp_directory_entry *entry, size_t entry_index) +static uint64_t relative_offset(uint32_t header_offset, uint64_t addr, uint64_t mode) { - amd_addr_mode mode = header->additional_info_fields.address_mode; - if (mode == AMD_ADDR_REL_BIOS) { - /* Entry address mode override directory mode with this value */ - mode = entry->address_mode; - } - switch (mode) { - case AMD_ADDR_REL_BIOS: - return entry->addr + header_offset; + /* Since this utility operates on the BIOS file, physical address is converted + relative to the start of the BIOS file. */ + case AMD_ADDR_PHYSICAL: + if (addr < SPI_ROM_BASE || addr > (SPI_ROM_BASE + FILE_REL_MASK)) { + ERR("Invalid address(%lx) or mode(%lx)\n", addr, mode); + /* TODO: fix amdfwtool to program the right address/mode. In guybrush, + * lots of addresses are marked as physical, but they are relative to + * BIOS. Until that is fixed, just leave an error message. */ + // exit(1); + } + return addr & FILE_REL_MASK; - case AMD_ADDR_REL_SLOT: - return entry->addr + header_offset + sizeof(psp_directory_header) + - entry_index * sizeof(psp_directory_entry); + case AMD_ADDR_REL_BIOS: + if (addr > FILE_REL_MASK) { + ERR("Invalid address(%lx) or mode(%lx)\n", addr, mode); + exit(1); + } + return addr & FILE_REL_MASK; + + case AMD_ADDR_REL_TAB: + return addr + header_offset; default: - break; + ERR("Unsupported mode %lu\n", mode); + exit(1); } - - return entry->addr & FILE_REL_MASK; } static int read_fw_header(FILE *fw, uint32_t offset, embedded_firmware *fw_header) @@ -120,9 +128,10 @@ for (size_t i = 0; i < num_current_entries; i++) { uint32_t type = current_entries[i].type; + uint64_t mode = current_entries[i].address_mode; + uint64_t addr = current_entries[i].addr; + if (type == AMD_PSP_FUSE_CHAIN) { - uint64_t mode = current_entries[i].address_mode; - uint64_t addr = current_entries[i].addr; uint64_t fuse = mode << 62 | addr; printf("Soft-fuse:0x%lx\n", fuse); @@ -132,8 +141,7 @@ if (l2_dir_offset != 0) return 1; - l2_dir_offset = relative_offset(&header, psp_offset, - &current_entries[i], i); + l2_dir_offset = relative_offset(psp_offset, addr, mode); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/66572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126 Gerrit-Change-Number: 66572 Gerrit-PatchSet: 16 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot
by Taniya Das (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Shelley Chen, Taniya Das, Venkat Thogaru, Julius Werner, Sudheer Amrabadi. Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68384 ) Change subject: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot ...................................................................... Patch Set 6: (2 comments) File src/soc/qualcomm/sc7280/socinfo.c: https://review.coreboot.org/c/coreboot/+/68384/comment/247bf8c3_5b82adc7 PS4, Line 12: static struct chipinfo chipinfolut[] = { > Not related directly to this patch, but just some general observations about this code: each entry h […] Changed structure members range uint32_t to uint16_t, in structure initialization instead of macros used designated initializers, here we are keeping chip_id, because we need it for future purpose use. https://review.coreboot.org/c/coreboot/+/68384/comment/0d4ac63b_5e4c4968 PS4, Line 57: return false; > Done. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Gerrit-Change-Number: 68384 Gerrit-PatchSet: 6 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 26 Oct 2022 15:53:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Enable CBFS Verification
by Raul Rangel (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Jason Glenesk, Jason Nien, Marshall Dawson, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66948 ) Change subject: mb/google/skyrim: Enable CBFS Verification ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd22a521a913705af0d2aca17acd1aa069a77f29 Gerrit-Change-Number: 66948 Gerrit-PatchSet: 14 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Oct 2022 15:52:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cbfs_verification: Remove dependency on VBOOT_STARTS_BEFORE_BOOTBLOCK
by Raul Rangel (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66947 ) Change subject: cbfs_verification: Remove dependency on VBOOT_STARTS_BEFORE_BOOTBLOCK ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a3254728a51a8ee7d7782afcea15ea06d93da7d Gerrit-Change-Number: 66947 Gerrit-PatchSet: 13 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 15:51:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL
by Nick Vaccaro (Code Review) 26 Oct '22

26 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Tim Wawrzynczak, Nick Vaccaro, Ivy Jian, Eric Lai. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68901 ) Change subject: soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Gerrit-Change-Number: 68901 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 26 Oct 2022 15:51:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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