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Change subject: soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto Engine
......................................................................
Patch Set 10:
(1 comment)
File src/soc/amd/common/psp_verstage/vboot_crypto.c:
https://review.coreboot.org/c/coreboot/+/68184/comment/2c24ba2d_b9f1db37
PS10, Line 98: CONFIG_VBOOT_HASH_BLOCK_SIZE
Hrmm, how large is this? Will this overflow the stack?
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Change subject: soc/amd/mendocino: Add GSVCD range
......................................................................
Patch Set 13: Code-Review+2
(1 comment)
File src/soc/amd/mendocino/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66945/comment/1f3234d3_c317e6a7
PS13, Line 333: BIOSL2
When we start passing a hash table to PSP of all the AMD FW, could we include the bootblock in that list?
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Change subject: soc/amd/mendocino: Update build rules for PSP BIOS image
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Change subject: soc/amd: Add amdfw.rom in coreboot.pre
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Patch Set 14: Code-Review+2
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Change subject: mb/google/brya: Update devicetree setting for lisbon
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Patch Set 4: Code-Review+2
(1 comment)
Patchset:
PS4:
FYI, Tim no longer works for Google, you can stop adding him as a reviewer on CLs.
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Change subject: util/amdfwtool/amdfwread: Update relative_offset function
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Patch Set 15: Code-Review+2
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Change subject: mb/google/brya/var/lisbon: use i2c1 for TPM for lisbon
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Change subject: mb/google/brask/var/lisbon: Update gpio table
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Change subject: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
......................................................................
cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
Pre-sandy bridge hardware is likely affected by the sinkhole
vulnerability.
Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/Kconfig
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37321/1
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index efb5fa9..335463d 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -139,9 +139,9 @@
config SMM_LAPIC_REMAP_MITIGATION
bool
- default y if NORTHBRIDGE_INTEL_I945
- default y if NORTHBRIDGE_INTEL_GM45
- default y if NORTHBRIDGE_INTEL_NEHALEM
+ default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \
+ || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \
+ || NORTHBRIDGE_INTEL_E7505
default n
config SERIALIZED_SMM_INITIALIZATION
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Change subject: lib/coreboot_table: Simplify API to set up lb_serial
......................................................................
Patch Set 8:
(1 comment)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/68768/comment/d76c9bf5_1d4ea314
PS8, Line 111: else
one last concern is should we do a check/assert here, and only add LB_TAG_CONSOLE_SERIAL8250MEM console if the type is known?
(in case if some get_lb_serial returned a struct with new type of console, or if they forgot to set the type to a valid value...)
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