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Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> LGTM but PSP release don't support this yet. […]
With signed verstage we might not be using it right away. Signed verstage can be marked as dependent on the concerned PSP release.
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Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
......................................................................
Patch Set 2:
(1 comment)
Patchset:
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LGTM but PSP release don't support this yet. Is it safe to merge without PSP support?
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Change subject: soc/intel/common/cse: Add `send_end_of_post_to_cse()` a public function
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/61519/comment/313fe685_6326b8c1
PS1, Line 496: send_end_of_post_to_cse
suggestion:
`cse_send_end_of_post`
fits better with the naming scheme here
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Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
Hmm, I'd rather not have SoC code that calls into a weak function in common code which then just calls back into SoC code... why add the proverbial middleman?
File src/soc/intel/alderlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/61518/comment/ff400799_bab61465
PS1, Line 83: /* Function to set D0I3 for all HECI devices */
: void soc_set_d0i3_for_heci(void)
: {
: unsigned int cse_dev[] = {
: PCH_DEVFN_CSE,
: PCH_DEVFN_CSE_2,
: PCH_DEVFN_CSE_3,
: PCH_DEVFN_CSE_4
: };
:
: for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
: if (!is_cse_devfn_visible(cse_dev[i]))
: continue;
:
: set_cse_device_state(cse_dev[i], DEV_IDLE);
: }
: }
:
Could this function just be moved to common code?
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Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/tigerlake/smihandler.c:
https://review.coreboot.org/c/coreboot/+/61457/comment/ac6f1983_f9808ee9
PS5, Line 19: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
: heci1_disable();
Since this is now supposed to use PMC IPC, can we move it outside of SMM ?
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Change subject: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/61455/comment/9de87bed_bd7c550c
PS5, Line 590: params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT);
I thought the point was letting coreboot do the disable, so this would be `0` ?
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Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
oops, I didn't mean to push this patch
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Change subject: soc/intel/cannonlake: Use SBI msg to disable HECI1
......................................................................
Patch Set 5: Code-Review+2
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