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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Kangheui Won, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61522
to look at the new patch set (#2).
Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
......................................................................
soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
This will allow verstage to write post codes.
BUG=b:215425753
TEST=Boot guybrush and verify PSP post codes are printed
22-01-31 15:12:03.214 (S3->S0)
22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270
---
M src/soc/amd/cezanne/psp_verstage/chipset.c
M src/soc/amd/cezanne/psp_verstage/svc.c
M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
3 files changed, 8 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/61522/2
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Raul Rangel has uploaded a new patch set (#2) to the change originally created by Kangheui Won. ( https://review.coreboot.org/c/coreboot/+/61368 )
Change subject: psp_verstage: add new svc for cezanne
......................................................................
psp_verstage: add new svc for cezanne
Add svc_set_platform_bootmode svc to cezanne. PSP will use this
information to select proper widevine keybox.
BUG=b:211058864
TEST=build guybrush
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630
---
M src/soc/amd/cezanne/psp_verstage/svc.c
M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
2 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/61368/2
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61368 )
Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 1:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:
https://review.coreboot.org/c/coreboot/+/61368/comment/81a16fa2_593ec95d
PS1, Line 144: CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check
> Reading the comment on the other CL, should we remove the values we aren't going to support? i.e. […]
May be add a comment on the side about unused boot modes in PSP verstage. That will keep the change as close to PSP release while still adding the clarity regarding which boot modes are supported.
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Change subject: psp_verstage: report developer mode to PSP
......................................................................
Patch Set 1: Code-Review+2
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Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 1: Code-Review+2
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Change subject: lib: Add a mutex
......................................................................
Patch Set 14:
(2 comments)
Patchset:
PS13:
> Let's not drag Google product schedules into this, that should not be relevant for an upstream desig […]
Ping Kyösti
File src/lib/mutex.c:
https://review.coreboot.org/c/coreboot/+/59320/comment/000003f9_2adb739d
PS13, Line 43: assert(_mutex_is_locked_smp(mutex));
> In test environments, `_mutex_is_locked_smp(mutex)` could be evaluated twice, first in the if-block […]
Are you just asking that I read the value into a variable? That's seems unnecessary here.
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Change subject: mb/google/brya/var/vell: Enable SaGv
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61464/comment/829be42f_57f68155
PS1, Line 10: #a52b9c3
> Number sign (#) not needed.
Done
https://review.coreboot.org/c/coreboot/+/61464/comment/12685378_10e33162
PS1, Line 14:
> Can you add […]
Done
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Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info
......................................................................
Patch Set 3: Code-Review+2
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Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info
......................................................................
Patch Set 3:
(1 comment)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/61521/comment/1bd0f1b2_7b40009e
PS2, Line 420:
> nit: new line
Done.
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