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Change subject: soc/intel/graphics: Add override api for graphics_get_memory_base()
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS7:
> > > In future platform, PCI config 0x18 still has memory bar but display memory may not same as memo […]
In future platform, PCI config 0x18 still has memory bar but display memory may not same as memory bar address.
=> Yes, it'll be in between with offsets.
Exactly, I also have the same question and if that offset/address is still as part of PCI configuration space, can't we use a Kconfig (select from SoC) and common code take care of passing the address from *new offset*. I really don't think we need SoC override.
=> The concern is the fixed offset can not cover all the case like below.
ex)
display memory = PCI config 0x18 + GTT size + fixed offset
GTT size can be updated based on UPD.
In that case using Kconfig offset can't support for different GTT size.
That's reason why we want to override function to make more flexible.
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Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 3: Code-Review+2
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Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:
https://review.coreboot.org/c/coreboot/+/61368/comment/df375246_7e499ff5
PS3, Line 331: Get
> Disclaimer: the comments are also copied from the header file in PSP release. […]
Ack
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Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 3:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:
https://review.coreboot.org/c/coreboot/+/61368/comment/1a2633e4_628e75ce
PS3, Line 331: Get
> Set?
Disclaimer: the comments are also copied from the header file in PSP release.
I think the subject here is the PSP since it has "from verstage". Though I agree that this is confusing :(
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Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
......................................................................
Patch Set 2: Code-Review+2
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Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 3:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:
https://review.coreboot.org/c/coreboot/+/61368/comment/c48241f6_1792a9b7
PS3, Line 331: Get
Set?
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Change subject: psp_verstage: report developer mode to PSP
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/psp_verstage/chipset.c:
https://review.coreboot.org/c/coreboot/+/61369/comment/0c740594_dee343e9
PS1, Line 39: svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER);
> The enum includes all internal states in the PSP. […]
Added comments in CB:61368.
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Change subject: psp_verstage: add new svc for cezanne
......................................................................
Patch Set 3:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h:
https://review.coreboot.org/c/coreboot/+/61368/comment/e72de923_150fb030
PS1, Line 144: CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check
> May be add a comment on the side about unused boot modes in PSP verstage. […]
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61368
to look at the new patch set (#3).
Change subject: psp_verstage: add new svc for cezanne
......................................................................
psp_verstage: add new svc for cezanne
Add svc_set_platform_bootmode svc to cezanne. PSP will use this
information to select proper widevine keybox.
BUG=b:211058864
TEST=build guybrush
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630
---
M src/soc/amd/cezanne/psp_verstage/svc.c
M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/61368/3
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Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> With signed verstage we might not be using it right away. […]
Yeah it's safe to merge it without PSP support. We never check the SVC error code, so we silently ignore the failure.
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