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Change in coreboot[master]: sc7280: Add clock driver
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47076 ) Change subject: sc7280: Add clock driver ...................................................................... sc7280: Add clock driver Add support for clock driver for SC7280 Change-Id: I73661f709091da0a6bada43d20fb3bf4fe20b81c --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/clock.h 5 files changed, 548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47076/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 33f6def..f94a425 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -7,11 +7,13 @@ bootblock-y += timer.c bootblock-y += spi.c bootblock-$(CONFIG_SC7280_QSPI) += qspi.c +bootblock-y += clock.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-$(CONFIG_SC7280_QSPI) += qspi.c +verstage-y += clock.c ################################################################################ romstage-y += cbmem.c @@ -22,6 +24,7 @@ romstage-y += mmu.c romstage-y += spi.c romstage-$(CONFIG_SC7280_QSPI) += qspi.c +romstage-y += clock.c ################################################################################ ramstage-y += soc.c @@ -29,6 +32,7 @@ ramstage-y += timer.c ramstage-y += spi.c ramstage-$(CONFIG_SC7280_QSPI) += qspi.c +ramstage-y += clock.c ################################################################################ diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index 9e04351..49c9e18 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/clock.h> #include <soc/mmu.h> #include <soc/qspi.h> @@ -8,4 +9,5 @@ { sc7280_mmu_init(); quadspi_init(37500 * KHz); + clock_init(); } diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c new file mode 100644 index 0000000..f8285ba --- /dev/null +++ b/src/soc/qualcomm/sc7280/clock.c @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <timer.h> +#include <types.h> + +#define DIV(div) (2 * div - 1) + +struct clock_config qup_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + } +}; + +struct clock_config qspi_core_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(6), + }, + { + .hz = 200 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(3), + }, + { + .hz = 400 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(1.5), + }, +}; + +struct clock_config qup_wrap_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 32 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 75, + .d_2 = 75, + }, + { + .hz = 48 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 4, + .n = 25, + .d_2 = 25, + }, + { + .hz = 64 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 16, + .n = 75, + .d_2 = 75, + }, + { + .hz = 96 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 25, + .d_2 = 25, + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(6), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, +}; + +static int clock_configure_gpll0(void) +{ + clrbits32(&gcc->gpll0.config_ctl_u1, + BIT(CLK_CTL_GPLL_BB_CAL_CORR_INDEX_SHFT)); + setbits32(&gcc->gpll0.config_ctl_u1, + BIT(CLK_CTL_GPLL_PCODE_OFFET_28) | + BIT(CLK_CTL_GPLL_PCODE_OFFET_29)); + + /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ + setbits32(&gcc->gpll0.user_ctl, + 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); + + return CB_SUCCESS; +} + +static int clock_configure_mnd(struct sc7280_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + struct sc7280_mnd_clock *mnd = (struct sc7280_mnd_clock *)clk; + setbits32(&clk->rcg_cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return CB_SUCCESS; +} + +static int clock_configure(struct sc7280_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg_cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return CB_SUCCESS; +} + +static bool clock_is_off(u32 *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + int count = 200; + + /* Set clock vote bit */ + setbits32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (count-- > 0) { + if (!clock_is_off(cbcr_addr)) + return CB_SUCCESS; + udelay(1); + } + return CB_ERR; +} + +static int clock_enable(void *cbcr_addr) +{ + int count = 200; + + /* Set clock enable bit */ + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (count-- > 0) { + if (!clock_is_off(cbcr_addr)) + return CB_SUCCESS; + udelay(1); + } + return CB_ERR; +} + +void clock_reset_aop(void) +{ + /* Bring AOP out of RESET */ + clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); +} + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure(&gcc->qspi_core, + qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core_cbcr); +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct sc7280_bcr *bcr = bcr_addr; + + if (reset) + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_SHFT)); + else + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_SHFT)); + + return CB_SUCCESS; +} + +void clock_configure_dfsr(int qup) +{ + int idx; + int s = qup % QUP_WRAP1_S0; + uint32_t reg_val; + struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr, + BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), + BIT(CLK_CTL_CMD_DFSR_SHFT)); + + for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { + reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (qup_wrap_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); + + if (qup_wrap_cfg[idx].m == 0) + continue; + + setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].n - qup_wrap_cfg[idx].m) + & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); + } +} + +void clock_configure_qup(int qup, uint32_t hz) +{ + int s = qup % QUP_WRAP1_S0; + struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clock_configure(&qup_clk->mnd_clk.clock, qup_cfg, hz, + ARRAY_SIZE(qup_cfg)); +} + +void clock_enable_qup(int qup) +{ + int s = qup % QUP_WRAP1_S0; + int clk_en_off = qup < QUP_WRAP1_S0 ? + QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); + struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + if(qup == 14 || qup == 15) + clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en, + (qup-1)); + else + clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en1, + clk_en_off); +} + +void clock_init(void) +{ + clock_configure_gpll0(); + + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_S_AHB_CLK_ENA); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 70d17be..ae31b1c 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -5,4 +5,8 @@ #include <stdint.h> +#define AOSS_CC_BASE 0x0C2A0000 +#define GCC_BASE 0x00100000 +#define QSPI_BASE 0x088DC000 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h new file mode 100644 index 0000000..947f262 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/clock.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <types.h> + +#ifndef __SOC_QUALCOMM_SC7280_CLOCK_H__ +#define __SOC_QUALCOMM_SC7280_CLOCK_H__ + +#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 +#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 +#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 +#define QUPV3_WRAP0_CORE_CLK_ENA 8 +#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 +#define QUPV3_WRAP1_CORE_CLK_ENA 19 +#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 +#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) + +#define SRC_XO_HZ (19200 * KHz) +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_600MHZ 1 +#define SRC_GPLL0_EVEN_300MHZ 6 + +#define AOP_RESET_SHFT 0 +#define RCG_MODE_DUAL_EDGE 2 + +#define SCALE_FREQ_SHFT 11 + +struct sc7280_clock { + u32 rcg_cmd; + u32 rcg_cfg; +}; + +struct sc7280_mnd_clock { + struct sc7280_clock clock; + u32 m; + u32 n; + u32 d_2; +}; + +struct sc7280_dfsr_clock { + u32 cmd_dfsr; + u8 _res0[0x20 - 0x1c]; + u32 perf_dfsr[8]; + u8 _res1[0x60 - 0x40]; + u32 perf_m_dfsr[8]; + u8 _res2[0xa0 - 0x80]; + u32 perf_n_dfsr[8]; + u8 _res3[0xe0 - 0xc0]; + u32 perf_d_dfsr[8]; + u8 _res4[0x130 - 0x100]; +}; + +struct sc7280_qupv3_clock { + u32 cbcr; + struct sc7280_mnd_clock mnd_clk; + struct sc7280_dfsr_clock dfsr_clk; +}; + +struct sc7280_gpll { + u32 mode; + u32 l_val; + u32 cal_l_val; + u32 user_ctl; + u32 user_ctl_u; + u32 user_Ctl_u1; + u32 config_ctl; + u32 config_ctl_u; + u32 config_ctl_u1; + u32 test_ctl; + u32 test_ctl_u; + u32 test_ctl_u1; + u8 _res[0x1000 - 0x30]; +}; + +struct sc7280_gcc { + struct sc7280_gpll gpll0; + u8 _res1[0x17000 - 0x1000]; + u32 qup_wrap0_bcr; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + struct sc7280_qupv3_clock qup_wrap0_s[8]; + u8 _res3[0x18000 - 0x1798c]; + u32 qup_wrap1_bcr; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + struct sc7280_qupv3_clock qup_wrap1_s[8]; + u8 _res4[0x23000 - 0x1898c]; + u32 qup_wrap0_core_cbcr; + u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; + struct sc7280_clock qup_wrap0_core_2x; + u8 _res5[0x23138 - 0x23014]; + u32 qup_wrap1_core_cbcr; + u32 qup_wrap1_core_cdivr; + u32 qup_wrap1_core_2x_cbcr; + struct sc7280_clock qup_wrap1_core_2x; + u8 _res6[0x4b000 - 0x2314c]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; + struct sc7280_clock qspi_core; + u8 _res7[0x52000 - 0x4b014]; + u32 apcs_clk_br_en; + u8 _res8[0x52008 - 0x52004]; + u32 apcs_clk_br_en1; + u8 _res9[0x1000000 - 0x5200c]; +}; +check_member(sc7280_gcc, qup_wrap0_bcr, 0x17000); +check_member(sc7280_gcc, qup_wrap1_bcr, 0x18000); +check_member(sc7280_gcc, qup_wrap1_core_cbcr, 0x23138); +check_member(sc7280_gcc, apcs_clk_br_en1, 0x52008); + +struct sc7280_aoss { + u8 _res0[0x50020]; + u32 aoss_cc_reset_status; + u8 _res1[0x5002C - 0x50024]; + u32 aoss_cc_apcs_misc; +}; +check_member(sc7280_aoss, aoss_cc_reset_status, 0x50020); +check_member(sc7280_aoss, aoss_cc_apcs_misc, 0x5002C); + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, + CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 +}; + +enum clk_ctl_gpll_config_ctl { + CLK_CTL_GPLL_BB_CAL_CORR_INDEX_SHFT = 14, + CLK_CTL_GPLL_PCODE_OFFET_28 = 28, + CLK_CTL_GPLL_PCODE_OFFET_29 = 29, +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_BMSK = 0x1, + CLK_CTL_BCR_BLK_SHFT = 0, +}; + +enum clk_ctl_dfsr { + CLK_CTL_CMD_DFSR_BMSK = 0x1, + CLK_CTL_CMD_DFSR_SHFT = 0, + CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP0_S6, + QUP_WRAP0_S7, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, + QUP_WRAP1_S6, + QUP_WRAP1_S7, +}; + +struct clock_config { + uint32_t hz; + uint8_t src; + uint8_t div; + uint16_t m; + uint16_t n; + uint16_t d_2; +}; + +static struct sc7280_gcc *const gcc = (void *)GCC_BASE; +static struct sc7280_aoss *const aoss = (void *)AOSS_CC_BASE; + +void clock_init(void); +void clock_reset_aop(void); +void clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_configure_qup(int qup, uint32_t hz); +void clock_enable_qup(int qup); +void clock_configure_dfsr(int qup); +void clock_last_reset_was_watchdog(void); + +#endif // __SOC_QUALCOMM_SC7280_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/47076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73661f709091da0a6bada43d20fb3bf4fe20b81c Gerrit-Change-Number: 47076 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: sc7280: Limit SPI-NOR size
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Hello Sajida Bhanu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47145 to review the following change. Change subject: sc7280: Limit SPI-NOR size ...................................................................... sc7280: Limit SPI-NOR size Limit SPI-NOR size to 8MB. Change-Id: I31f788b5280636aca3e7e557db3e9ee53320d50d Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/drivers/spi/stmicro.c M src/mainboard/google/herobrine/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47145/1 diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 4cd8c1b..b02edf6 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -189,7 +189,7 @@ { /* N25Q256..1E */ .id[0] = STM_ID_N25Q256__1E, - .nr_sectors_shift = 13, + .nr_sectors_shift = 11, }, }; diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index 92f77db..b92136d 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -14,7 +14,7 @@ select RTC select SOC_QUALCOMM_SC7280 select SPI_FLASH - select SPI_FLASH_WINBOND + select SPI_FLASH_STMICRO select MAINBOARD_HAS_CHROMEOS config VBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/47145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f788b5280636aca3e7e557db3e9ee53320d50d Gerrit-Change-Number: 47145 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU
by Maxim Polyakov (Code Review) 17 Mar '22

17 Mar '22

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39374 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39374/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 40cd39b..0375cec 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,46 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + + /* Select primary GPU device */ + enum { + PRIMARY_AUTO = 0, /* Default */ + PRIMARY_IGD = 2, + PRIMARY_PCI = 3, + } primary_gpu; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 05cd0db..1576802 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,12 +264,34 @@ } } +static void soc_gpu_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + + m_cfg->PrimaryVideoAdaptor = soc_cfg->primary_gpu; + if (dev && dev->enabled && (soc_cfg->primary_gpu != PRIMARY_PCI)) { + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; + } +} + static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); /* @@ -307,6 +329,7 @@ check_full_retrain(mupd); fill_console_params(mupd); + soc_gpu_init_params(mupd); if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); -- To view, visit https://review.coreboot.org/c/coreboot/+/39374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Gerrit-Change-Number: 39374 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 51

Change in coreboot[master]: src/*: Make PCI ID macro names shorter
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39331 ) Change subject: src/*: Make PCI ID macro names shorter ...................................................................... src/*: Make PCI ID macro names shorter This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_. Used commands: find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/' {} \; find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/' {} \; Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 --- M src/device/pci_rom.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/dec/21143/21143.c M src/drivers/generic/bayhub/bh720.c M src/drivers/intel/gma/opregion.c M src/drivers/intel/i210/i210.c M src/drivers/intel/ish/ish.c M src/drivers/intel/wifi/wifi.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/xgi/common/XGI_main.h M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/z9s/z9s.c M src/include/device/pci_ids.h M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/iommu.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/iommu.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/iommu.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/gma.c M src/soc/amd/common/block/hda/hda.c M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/sata/sata.c M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/usb.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/usb.c M src/soc/cavium/common/pci/uart.c M src/soc/intel/apollolake/report_platform.c M src/soc/intel/baytrail/ehci.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/baytrail/pcie.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/sd.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/xhci.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/braswell/pcie.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/xhci.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/vr_config.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/quark/ehci.c M src/soc/intel/quark/gpio_i2c.c M src/soc/intel/quark/lpc.c M src/soc/intel/quark/northcluster.c M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi.c M src/soc/intel/quark/uart.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/tigerlake/bootblock/report_platform.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/ide.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/pci.c M src/southbridge/amd/agesa/hudson/pcie.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/ide.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/pci.c M src/southbridge/amd/pi/hudson/pcie.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/usb.c M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/ide.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/pci.c M src/southbridge/intel/i82801dx/usb.c M src/southbridge/intel/i82801dx/usb2.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/nic.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/pci.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/pci.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h 228 files changed, 4,921 insertions(+), 4,921 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Gerrit-Change-Number: 39331 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

12 47

Change in coreboot[master]: drivers/system76/dgpu: Add driver for System76 switchable graphics
by Jeremy Soller (Code Review) 04 Mar '22

04 Mar '22

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43615 ) Change subject: drivers/system76/dgpu: Add driver for System76 switchable graphics ...................................................................... drivers/system76/dgpu: Add driver for System76 switchable graphics This adds a driver for System76 systems with switchable NVIDIA graphics. The driver provides ACPI support for dynamically powering on and off the GPU, a function for enabling the GPU power in the bootblock, and a hook in ramstage for moving GPU prefetch resources above 4 GiB. Tested on system76/addw2, system76/gaze15, and system76/oryp6, which will be submitted in future patches. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I05833e88457bfc3612cc9a8cbf1eec68dcfc5566 --- A src/drivers/system76/dgpu/Kconfig A src/drivers/system76/dgpu/Makefile.inc A src/drivers/system76/dgpu/acpi/dgpu.asl A src/drivers/system76/dgpu/bootblock.c A src/drivers/system76/dgpu/ramstage.c 5 files changed, 313 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/43615/1 diff --git a/src/drivers/system76/dgpu/Kconfig b/src/drivers/system76/dgpu/Kconfig new file mode 100644 index 0000000..5096671 --- /dev/null +++ b/src/drivers/system76/dgpu/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_SYSTEM76_DGPU + bool + default n + help + System76 switchable graphics support diff --git a/src/drivers/system76/dgpu/Makefile.inc b/src/drivers/system76/dgpu/Makefile.inc new file mode 100644 index 0000000..a230f97 --- /dev/null +++ b/src/drivers/system76/dgpu/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_SYSTEM76_DGPU) += ramstage.c diff --git a/src/drivers/system76/dgpu/acpi/dgpu.asl b/src/drivers/system76/dgpu/acpi/dgpu.asl new file mode 100644 index 0000000..a721934 --- /dev/null +++ b/src/drivers/system76/dgpu/acpi/dgpu.asl @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (\_SB.PCI0.PEGP) { + Name (_ADR, 0x00010000) + + PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON) { + Debug = "PEGP.PWRR._ON" + If (_STA != 1) { + \_SB.PCI0.PEGP.DEV0._ON () + _STA = 1 + } + } + + Method (_OFF) { + Debug = "PEGP.PWRR._OFF" + If (_STA != 0) { + \_SB.PCI0.PEGP.DEV0._OFF () + _STA = 0 + } + } + } + + Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR }) + Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR }) + Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR }) +} + +Device (\_SB.PCI0.PEGP.DEV0) { + Name(_ADR, 0x00000000) + Name (_STA, 0xF) + Name (LTRE, 0) + + // Memory mapped PCI express registers + // Not sure what this stuff is, but it is used to get into GC6 + OperationRegion (RPCX, SystemMemory, 0xE0008000, 0x1000) + Field (RPCX, ByteAcc, NoLock, Preserve) { + PVID, 16, + PDID, 16, + CMDR, 8, + Offset (0x19), + PRBN, 8, + Offset (0x84), + D0ST, 2, + Offset (0xAA), + CEDR, 1, + Offset (0xAC), + , 4, + CMLW, 6, + Offset (0xB0), + ASPM, 2, + , 2, + P0LD, 1, + RTLK, 1, + Offset (0xC9), + , 2, + LREN, 1, + Offset (0x11A), + , 1, + VCNP, 1, + Offset (0x214), + Offset (0x216), + P0LS, 4, + Offset (0x248), + , 7, + Q0L2, 1, + Q0L0, 1, + Offset (0x504), + Offset (0x506), + PCFG, 2, + Offset (0x508), + TREN, 1, + Offset (0xC20), + , 4, + P0AP, 2, + Offset (0xC38), + , 3, + P0RM, 1, + Offset (0xC74), + P0LT, 4, + Offset (0xD0C), + , 20, + LREV, 1 + } + + Method (_ON) { + Debug = "PEGP.DEV0._ON" + + If (_STA != 0xF) { + Debug = " If DGPU_PWR_EN low" + If (! GTXS (DGPU_PWR_EN)) { + Debug = " DGPU_PWR_EN high" + STXS (DGPU_PWR_EN) + + Debug = " Sleep 16" + Sleep (16) + } + + Debug = " DGPU_RST_N high" + STXS(DGPU_RST_N) + + Debug = " Sleep 10" + Sleep (10) + + Debug = " Q0L0 = 1" + Q0L0 = 1 + + Debug = " Sleep 16" + Sleep (16) + + Debug = " While Q0L0" + Local0 = 0 + While (Q0L0) { + If ((Local0 > 4)) { + Debug = " While Q0L0 timeout" + Break + } + + Sleep (16) + Local0++ + } + + Debug = " P0RM = 0" + P0RM = 0 + + Debug = " P0AP = 0" + P0AP = 0 + + Debug = Concatenate(" LREN = ", ToHexString(LTRE)) + LREN = LTRE + + Debug = " CEDR = 1" + CEDR = 1 + + Debug = " CMDR |= 7" + CMDR |= 7 + + Debug = " _STA = 0xF" + _STA = 0xF + } + } + + Method (_OFF) { + Debug = "PEGP.DEV0._OFF" + + If (_STA != 0x5) { + Debug = Concatenate(" LTRE = ", ToHexString(LREN)) + LTRE = LREN + + Debug = " Q0L2 = 1" + Q0L2 = 1 + + Debug = " Sleep 16" + Sleep (16) + + Debug = " While Q0L2" + Local0 = Zero + While (Q0L2) { + If ((Local0 > 4)) { + Debug = " While Q0L2 timeout" + Break + } + + Sleep (16) + Local0++ + } + + Debug = " P0RM = 1" + P0RM = 1 + + Debug = " P0AP = 3" + P0AP = 3 + + Debug = " Sleep 10" + Sleep (10) + + Debug = " DGPU_RST_N low" + CTXS(DGPU_RST_N) + + Debug = " While DGPU_GC6 low" + Local0 = Zero + While (! GRXS(DGPU_GC6)) { + If ((Local0 > 4)) { + Debug = " While DGPU_GC6 low timeout" + + Debug = " DGPU_PWR_EN low" + CTXS (DGPU_PWR_EN) + Break + } + + Sleep (16) + Local0++ + } + + Debug = " _STA = 0x5" + _STA = 0x5 + } + } +} diff --git a/src/drivers/system76/dgpu/bootblock.c b/src/drivers/system76/dgpu/bootblock.c new file mode 100644 index 0000000..61f7fbf --- /dev/null +++ b/src/drivers/system76/dgpu/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//TODO: do not require this to be included in mainboard bootblock.c + +#include <console/console.h> +#include <delay.h> +#include <gpio.h> + +static void dgpu_power_enable(int onoff) { + printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff); + if (onoff) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + mdelay(4); + gpio_set(DGPU_RST_N, 1); + } else { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 0); + } + mdelay(50); +} diff --git a/src/drivers/system76/dgpu/ramstage.c b/src/drivers/system76/dgpu/ramstage.c new file mode 100644 index 0000000..eeb1607 --- /dev/null +++ b/src/drivers/system76/dgpu/ramstage.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci.h> + +static void dgpu_read_resources(struct device *dev) { + printk(BIOS_INFO, "system76: dgpu_read_resources %s\n", dev_path(dev)); + + pci_dev_read_resources(dev); + + int bar; + // Find all BARs on DGPU, mark them above 4g if prefetchable + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { + printk(BIOS_INFO, " BAR at 0x%02x\n", bar); + + struct resource *res; + res = probe_resource(dev, bar); + if (res) { + if (res->flags & IORESOURCE_PREFETCH) { + printk(BIOS_INFO, " marked above 4g\n"); + res->flags |= IORESOURCE_ABOVE_4G; + } else { + printk(BIOS_INFO, " not prefetch\n"); + } + } else { + printk(BIOS_INFO, " not found\n"); + } + } +} + +static void dgpu_enable_resources(struct device *dev) { + printk(BIOS_INFO, "system76: dgpu_enable_resources %s\n", dev_path(dev)); + + dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID; + dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID; + printk(BIOS_INFO, " subsystem <- %04x/%04x\n", dev->subsystem_vendor, dev->subsystem_device); + pci_write_config32(dev, 0x40, ((dev->subsystem_device & 0xffff) << 16) | (dev->subsystem_vendor & 0xffff)); + + pci_dev_enable_resources(dev); +} + +static struct device_operations dgpu_pci_ops_dev = { + .read_resources = dgpu_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = dgpu_enable_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = pci_rom_write_acpi_tables, + .acpi_fill_ssdt = pci_rom_ssdt, +#endif + .init = pci_dev_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static void dgpu_above_4g(void *unused) { + struct device *pdev; + + // Find PEG0 + pdev = pcidev_on_root(1, 0); + if (!pdev) { + printk(BIOS_ERR, "system76: failed to find PEG0\n"); + return; + } + printk(BIOS_INFO, "system76: PEG0 at %p, %04x:%04x\n", pdev, pdev->vendor, pdev->device); + + int fn; + for (fn = 0; fn < 8; fn++) { + struct device *dev; + + // Find DGPU functions + dev = pcidev_path_behind(pdev->link_list, PCI_DEVFN(0, fn)); + if (dev) { + printk(BIOS_INFO, "system76: DGPU fn %d at %p, %04x:%04x\n", fn, dev, dev->vendor, dev->device); + dev->ops = &dgpu_pci_ops_dev; + } else { + printk(BIOS_ERR, "system76: failed to find DGPU fn %d\n", fn); + } + } +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, dgpu_above_4g, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/43615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05833e88457bfc3612cc9a8cbf1eec68dcfc5566 Gerrit-Change-Number: 43615 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[4.11_branch]: cpu/amd/car: Remove C source incldue of disable_cache_as_ram.c
by Michał Żygowski (Code Review) 17 Feb '22

17 Feb '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48464 ) Change subject: cpu/amd/car: Remove C source incldue of disable_cache_as_ram.c ...................................................................... cpu/amd/car: Remove C source incldue of disable_cache_as_ram.c Change-Id: Ib4841756127a3a28e400f4ad4bd58786dd343739 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/cpu/amd/car/disable_cache_as_ram.c M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/Makefile.inc M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/include/cpu/amd/car.h M src/include/cpu/amd/model_10xxx_rev.h 6 files changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48464/1 diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index fb632bb..0ef50f9 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -15,10 +15,14 @@ #include <arch/cpu.h> #include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/car.h> +#include <cpu/amd/model_10xxx_rev.h> -static __always_inline uint32_t amd_fam1x_cpu_family(void) +uint32_t amd_fam1x_cpu_family(void) { uint32_t family; @@ -28,7 +32,6 @@ return family; } -static __always_inline void disable_cache_as_ram_real(uint8_t skip_sharedc_config) { msr_t msr; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 78e417f..0eb8906 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -16,16 +16,16 @@ #include <arch/stages.h> #include <arch/early_variables.h> #include <commonlib/helpers.h> +#include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <cpu/amd/msr.h> +#include <cpu/amd/model_10xxx_rev.h> #include <arch/acpi.h> #include <program_loading.h> #include <romstage_handoff.h> -#include "cpu/amd/car/disable_cache_as_ram.c" - // For set_sysinfo_in_ram() #include <northbridge/amd/amdfam10/raminit.h> @@ -118,7 +118,7 @@ asmlinkage void cache_as_ram_new_stack(void) { print_car_debug("Disabling cache as RAM now\n"); - disable_cache_as_ram_real(0); // inline + disable_cache_as_ram_real(0); disable_cache(); /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index f116042..2bc2abb 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -1,5 +1,6 @@ romstage-y += ../../x86/mtrr/earlymtrr.c romstage-y += ../car/post_cache_as_ram.c +romstage-y += ../car/disable_cache_as_ram.c romstage-y += init_cpus.c romstage-y += fidvid.c diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 61598d2..f56ee93 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -27,7 +27,9 @@ #include <northbridge/amd/amdht/AsPsDefs.h> #include <northbridge/amd/amdht/porting.h> #include <northbridge/amd/amdht/h3ncmn.h> +#include <cpu/amd/car.h> #include <cpu/amd/family_10h-family_15h/fidvid.h> +#include <cpu/amd/model_10xxx_rev.h> #include <southbridge/amd/common/reset.h> #if CONFIG(SOUTHBRIDGE_AMD_SB700) @@ -38,8 +40,6 @@ #include <southbridge/amd/sb800/sb800.h> #endif -#include "cpu/amd/car/disable_cache_as_ram.c" - #if CONFIG(PCI_IO_CFG_EXT) static void set_EnableCf8ExtCfg(void) { @@ -326,7 +326,7 @@ msr_t msr; uint32_t family; - family = amd_fam1x_cpu_family(); // inline + family = amd_fam1x_cpu_family(); if (family < 0x6f) { /* Family 10h or earlier */ @@ -353,7 +353,7 @@ } } - disable_cache_as_ram_real(skip_sharedc_config); // inline + disable_cache_as_ram_real(skip_sharedc_config); /* Mark the core as sleeping */ lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_ASLEEP); diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 359fa6b..c11ce7c 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -6,6 +6,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); asmlinkage void *post_cache_as_ram(void); asmlinkage void cache_as_ram_new_stack(void); +void disable_cache_as_ram_real(uint8_t skip_sharedc_config); void disable_cache_as_ram(void); diff --git a/src/include/cpu/amd/model_10xxx_rev.h b/src/include/cpu/amd/model_10xxx_rev.h index 88d395e..4b37baa 100644 --- a/src/include/cpu/amd/model_10xxx_rev.h +++ b/src/include/cpu/amd/model_10xxx_rev.h @@ -17,7 +17,7 @@ #define __CPU_AMD_MODEL_10XXX_REV_H__ int init_processor_name(void); - +uint32_t amd_fam1x_cpu_family(void); /* place holder for Family 10 revision code */ #endif /* __CPU_AMD_MODEL_10XXX_REV_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ib4841756127a3a28e400f4ad4bd58786dd343739 Gerrit-Change-Number: 48464 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[4.11_branch]: cpu/amd/quadcore: Remove C source includes
by Michał Żygowski (Code Review) 17 Feb '22

17 Feb '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48462 ) Change subject: cpu/amd/quadcore: Remove C source includes ...................................................................... cpu/amd/quadcore: Remove C source includes TEST=build test KGPE-D16 Change-Id: Iba68d0da5371f0e0f0b7dcf96660d80874a8fbc2 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/cpu/amd/quadcore/Makefile.inc M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/amd/quadcore/quadcore.c M src/cpu/amd/quadcore/quadcore_id.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c 27 files changed, 10 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/48462/1 diff --git a/src/cpu/amd/quadcore/Makefile.inc b/src/cpu/amd/quadcore/Makefile.inc index c390b4e..9fe4063 100644 --- a/src/cpu/amd/quadcore/Makefile.inc +++ b/src/cpu/amd/quadcore/Makefile.inc @@ -1 +1,4 @@ +romstage-y += quadcore.c +romstage-y += quadcore_id.c + ramstage-y += amd_sibling.c diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index ac637ff..6b6e17b 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -22,14 +22,8 @@ #include <cpu/amd/msr.h> #include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/amdfam10_sysconf.h> - -extern struct device *get_node_pci(u32 nodeid, u32 fn); - -#if 0 -static int first_time = 1; -#endif - -#include "quadcore_id.c" +#include <cpu/amd/multicore.h> +#include <northbridge/amd/amdfam10/amdfam10.h> static u32 get_max_siblings(u32 nodes) { diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 8125fb4..454462f 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -15,12 +15,14 @@ #include <console/console.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <cpu/amd/multicore.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <northbridge/amd/amdfam10/amdfam10.h> + #if CONFIG(HAVE_OPTION_TABLE) #include "option_table.h" #endif -#include "cpu/amd/quadcore/quadcore_id.c" - u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 2c4d60d..c518fb4 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -16,6 +16,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/multicore.h> #include <device/pci_ops.h> +#include <northbridge/amd/amdfam10/amdfam10.h> //called by bus_cpu_scan too u32 read_nb_cfg_54(void) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 0589a0b..3083daa 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -38,8 +38,6 @@ #include "southbridge/amd/sb800/early_setup.c" #include <arch/early_variables.h> #include <cbmem.h> - -#include "cpu/amd/quadcore/quadcore.c" #include "spd.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 909f33e..46aaf22 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -38,8 +38,6 @@ #include "southbridge/amd/sb800/early_setup.c" #include <spd.h> -#include "cpu/amd/quadcore/quadcore.c" - int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 3397d26..9509e24 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -43,8 +43,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#include "cpu/amd/quadcore/quadcore.c" - int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 3871c59..c556a90 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -37,8 +37,6 @@ #include "southbridge/amd/amd8111/early_smbus.c" #include "southbridge/amd/amd8111/early_ctrl.c" -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 702e9db..a72788a 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -39,8 +39,6 @@ #include <spd.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 51d178f..79e8f7d 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -45,8 +45,6 @@ #include <cbmem.h> #include <types.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 7d710d7..a90e078 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -41,8 +41,6 @@ #include <northbridge/amd/amdfam10/raminit.h> #include <cpu/amd/family_10h-family_15h/init_cpus.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) #define CK804_MB_SETUP \ diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 637ec42..3d95e74 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -46,8 +46,6 @@ #include <cbmem.h> #include <types.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index c52b35b..c0de18c 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -41,8 +41,6 @@ #include <spd.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index b7af9e2..3a2a6d9 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -41,8 +41,6 @@ #include <spd.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 52de343..99abd6f 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -41,8 +41,6 @@ #include "southbridge/amd/sb800/early_setup.c" #include "spd.h" -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 8d7366e..dbf0afc 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -39,8 +39,6 @@ #include <southbridge/amd/rs780/rs780.h> #include <southbridge/amd/sb800/early_setup.c> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 0d1f45d..ec34ac4 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -41,8 +41,6 @@ #include <spd.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 384eccd..651a2a5 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -41,8 +41,6 @@ #include <spd.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 48af367..bee2fe4 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -41,8 +41,6 @@ #include <cbmem.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 1b91e97e..4a8540c 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -46,8 +46,6 @@ #include "southbridge/broadcom/bcm5785/early_smbus.c" #include "southbridge/broadcom/bcm5785/early_setup.c" -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index d8afd67..367e83a 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -41,8 +41,6 @@ #include <cbmem.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 33d40b8..78e2337 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -42,8 +42,6 @@ #include <cbmem.h> #include <southbridge/amd/rs780/rs780.h> -#include "cpu/amd/quadcore/quadcore.c" - #if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2) #else diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 4658d75..b17e878 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -40,8 +40,6 @@ #include <southbridge/amd/common/reset.h> #include <southbridge/nvidia/mcp55/mcp55.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 6f6ac71..ca75186 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -39,8 +39,6 @@ #include <cbmem.h> #include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN - -#include "cpu/amd/quadcore/quadcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 7c489ca..560903d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -39,8 +39,6 @@ #include <arch/early_variables.h> #include <cbmem.h> #include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN - -#include "cpu/amd/quadcore/quadcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 302e86f..e942918 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -40,8 +40,6 @@ #include <arch/early_variables.h> #include <cbmem.h> -#include "cpu/amd/quadcore/quadcore.c" - int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index c546a33..1aff429 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -39,8 +39,6 @@ #include <cbmem.h> #include <southbridge/nvidia/mcp55/mcp55.h> -#include "cpu/amd/quadcore/quadcore.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -- To view, visit https://review.coreboot.org/c/coreboot/+/48462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iba68d0da5371f0e0f0b7dcf96660d80874a8fbc2 Gerrit-Change-Number: 48462 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide
by Michał Żygowski (Code Review) 17 Feb '22

17 Feb '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48461 ) Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ...................................................................... src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide Change-Id: I6c2c25ce6dc82b8f5bf9d41eb5cecd3b3274d032 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/quadcore/quadcore_id.c M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/sr5650/cmn.h 5 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/48461/1 diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index a1dc1f4..08cca13 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -65,7 +65,7 @@ if (is_fam15h()) { enable_cc6 = 0; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18)) enable_cc6 = 1; #else diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 7ec1bdb..ccc8c44 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -42,7 +42,7 @@ uint32_t family; uint32_t model; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); #else f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); @@ -109,7 +109,7 @@ uint32_t f5x84; uint8_t core_count; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84); #else f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84); diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 23e9232..8975641 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -21,7 +21,7 @@ #include "raminit.h" #include <northbridge/amd/amdmct/amddefs.h> -#if !ENV_PCI_SIMPLE_DEVICE +#if !__SIMPLE_DEVICE__ u32 Get_NB32(u32 dev, u32 reg) { return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 52032e9..8cb8c58 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -69,7 +69,7 @@ return s3nv_region.region.offset; } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static uint32_t read_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg) #else @@ -79,7 +79,7 @@ { if (is_fam15h()) { uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -98,7 +98,7 @@ return pci_read_config32(dev, reg); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static void write_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg, uint32_t value) #else @@ -108,7 +108,7 @@ { if (is_fam15h()) { uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -127,7 +127,7 @@ pci_write_config32(dev, reg, value); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static uint32_t read_amd_dct_index_register(pci_devfn_t dev, uint32_t index_ctl_reg, uint32_t index) #else @@ -147,7 +147,7 @@ return dword; } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static uint32_t read_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index) #else @@ -158,7 +158,7 @@ { if (is_fam15h()) { uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 9588105..ef66a5d 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -34,7 +34,7 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4) -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) #else static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) @@ -44,7 +44,7 @@ return pci_read_config32(dev, index_reg + 0x4); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) #else @@ -56,7 +56,7 @@ pci_write_config32(dev, index_reg + 0x4, data); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) @@ -65,7 +65,7 @@ return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmisc_write_index(struct device *nb_dev, u32 index, @@ -75,7 +75,7 @@ nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -92,7 +92,7 @@ } } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 htiu_read_index(struct device *nb_dev, u32 index) @@ -101,7 +101,7 @@ return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) @@ -110,7 +110,7 @@ nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) @@ -119,7 +119,7 @@ return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) @@ -128,7 +128,7 @@ nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -145,7 +145,7 @@ } } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -162,7 +162,7 @@ } } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) #else @@ -179,7 +179,7 @@ } } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -196,7 +196,7 @@ } } -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, u32 val) #else -- To view, visit https://review.coreboot.org/c/coreboot/+/48461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6c2c25ce6dc82b8f5bf9d41eb5cecd3b3274d032 Gerrit-Change-Number: 48461 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: northbridge/amd/amdfam10: remove C include of inline_helper.c
by Michał Żygowski (Code Review) 17 Feb '22

17 Feb '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48465 ) Change subject: northbridge/amd/amdfam10: remove C include of inline_helper.c ...................................................................... northbridge/amd/amdfam10: remove C include of inline_helper.c Change-Id: I5ecd809e9597304ee4b0ff043e1d32abb4eca65e Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/amdfam10_util.c D src/northbridge/amd/amdfam10/inline_helper.c 3 files changed, 21 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48465/1 diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index ad8d013..b5446b2 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -18,10 +18,10 @@ #define AMDFAM10_H #include <stdint.h> +#include <arch/cpu.h> #include <device/device.h> #include "early_ht.h" -#include "inline_helper.c" struct DCTStatStruc; struct MCTStatStruc; @@ -1022,4 +1022,6 @@ struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(struct device *device); +uint8_t is_fam15h(void); + #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 3e8c2fb..cdc7044 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -18,8 +18,25 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include "raminit.h" #include <northbridge/amd/amdmct/amddefs.h> +#include <northbridge/amd/amdfam10/amdfam10.h> + +#include "raminit.h" + +uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} #ifndef __SIMPLE_DEVICE__ u32 Get_NB32(u32 dev, u32 reg) diff --git a/src/northbridge/amd/amdfam10/inline_helper.c b/src/northbridge/amd/amdfam10/inline_helper.c deleted file mode 100644 index 7f26031..0000000 --- a/src/northbridge/amd/amdfam10/inline_helper.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> - -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I5ecd809e9597304ee4b0ff043e1d32abb4eca65e Gerrit-Change-Number: 48465 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: cpu/amd/family_10h-family_15h: Remove fidvid.c include
by Michał Żygowski (Code Review) 17 Feb '22

17 Feb '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48463 ) Change subject: cpu/amd/family_10h-family_15h: Remove fidvid.c include ...................................................................... cpu/amd/family_10h-family_15h: Remove fidvid.c include Do bare minimum to remove the C source include. The migrated functions maybe are not in the right places for now, but will be regrouped in further patches. TEST=build tested KGPE-D16 Change-Id: I74b2784b27e7e8664ebf842173d57841602bef3e Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/cpu/amd/family_10h-family_15h/Makefile.inc M src/cpu/amd/family_10h-family_15h/fidvid.c A src/cpu/amd/family_10h-family_15h/fidvid.h M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/amd/quadcore/quadcore.c M src/include/cpu/amd/multicore.h 7 files changed, 57 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48463/1 diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc index 7035323..f116042 100644 --- a/src/cpu/amd/family_10h-family_15h/Makefile.inc +++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -2,6 +2,7 @@ romstage-y += ../car/post_cache_as_ram.c romstage-y += init_cpus.c +romstage-y += fidvid.c ramstage-y += model_10xxx_init.c ramstage-y += processor_name.c diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 57207a4..a2140a1 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -88,9 +88,13 @@ #include <console/console.h> #include <cpu/amd/msr.h> +#include <cpu/amd/multicore.h> #include <device/pci_ops.h> #include <stdint.h> #include <northbridge/amd/amdht/AsPsDefs.h> +#include <northbridge/amd/amdht/ht_wrapper.h> +#include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <cpu/amd/family_10h-family_15h/fidvid.h> #include <stdlib.h> static inline void print_debug_fv(const char *str, u32 val) @@ -861,7 +865,7 @@ } -static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) +void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) { u32 send; diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.h b/src/cpu/amd/family_10h-family_15h/fidvid.h new file mode 100644 index 0000000..fe092fb --- /dev/null +++ b/src/cpu/amd/family_10h-family_15h/fidvid.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); \ No newline at end of file diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 452f7ce..61598d2 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -27,7 +27,7 @@ #include <northbridge/amd/amdht/AsPsDefs.h> #include <northbridge/amd/amdht/porting.h> #include <northbridge/amd/amdht/h3ncmn.h> - +#include <cpu/amd/family_10h-family_15h/fidvid.h> #include <southbridge/amd/common/reset.h> #if CONFIG(SOUTHBRIDGE_AMD_SB700) @@ -142,7 +142,7 @@ //core range = 1 : core 0 only //core range = 2 : cores other than core0 -static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, +void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, process_ap_t process_ap, void *gp) { // here assume the OS don't change our apicid @@ -202,7 +202,7 @@ } } -static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) +int lapic_remote_read(int apicid, int reg, u32 *pvalue) { int timeout; u32 status; @@ -231,10 +231,6 @@ return result; } -#if CONFIG(SET_FIDVID) -static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); -#endif - static __always_inline void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) @@ -774,32 +770,6 @@ } } -static u32 get_platform_type(void) -{ - u32 ret = 0; - - switch (SYSTEM_TYPE) { - case 1: - ret |= AMD_PTYPE_DSK; - break; - case 2: - ret |= AMD_PTYPE_MOB; - break; - case 0: - ret |= AMD_PTYPE_SVR; - break; - default: - break; - } - - /* FIXME: add UMA support. */ - - /* All Fam10 are multi core */ - ret |= AMD_PTYPE_MC; - - return ret; -} - static void AMD_SetupPSIVID_d(u32 platform_type, u8 node) { u32 dword; @@ -835,7 +805,7 @@ * * Returns the offset of the link register. */ -static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset) +BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset) { u32 reg; u32 val; @@ -875,7 +845,7 @@ * * Returns the link characteristic mask. */ -static u32 AMD_checkLinkType(u8 node, u8 regoff) +u32 AMD_checkLinkType(u8 node, u8 regoff) { uint32_t val; uint32_t val2; @@ -1882,7 +1852,3 @@ } #endif } - -#if CONFIG(SET_FIDVID) -# include "fidvid.c" -#endif diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index 4be6ee8..5fb6134 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -39,6 +39,11 @@ uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); void start_other_cores(uint32_t bsp_apicid); u32 get_core_num_in_bsp(u32 nodeid); +int lapic_remote_read(int apicid, int reg, u32 *pvalue); +BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset); +u32 AMD_checkLinkType(u8 node, u8 regoff); +void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, + process_ap_t process_ap, void *gp); void update_microcode(u32 cpu_deviceid); diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 454462f..3311d8d 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -23,6 +23,32 @@ #include "option_table.h" #endif +u32 get_platform_type(void) +{ + u32 ret = 0; + + switch (SYSTEM_TYPE) { + case 1: + ret |= AMD_PTYPE_DSK; + break; + case 2: + ret |= AMD_PTYPE_MOB; + break; + case 0: + ret |= AMD_PTYPE_SVR; + break; + default: + break; + } + + /* FIXME: add UMA support. */ + + /* All Fam10 are multi core */ + ret |= AMD_PTYPE_MC; + + return ret; +} + u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index 79bea66..c7b28a6 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -39,5 +39,6 @@ void wait_all_other_cores_stopped(uint32_t bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); u32 get_initial_apicid(void); +u32 get_platform_type(void); #endif /* CPU_AMD_QUADCORE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I74b2784b27e7e8664ebf842173d57841602bef3e Gerrit-Change-Number: 48463 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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