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Change subject: security/vboot/secdata_tpm: Setup space for widevine counter info
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61521/comment/1627a85d_4e1ffe01
PS1, Line 7: Setup
Set up
https://review.coreboot.org/c/coreboot/+/61521/comment/b4c10022_4ae16572
PS1, Line 10: created the space for widevine counters.
So the space is 64 bytes or kB big?
https://review.coreboot.org/c/coreboot/+/61521/comment/db03e110_80f3001f
PS1, Line 14: and initialized to 0.
What command does that?
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Change subject: mb/amd/chausie: update GPIO for chausie
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61461/comment/901a58cd_dc55cb31
PS3, Line 9: Initial filling out GPIOs for chausie mainboard.
nit: I might phrase the message body differently. Maybe something like "Add/update initial GPIO pin descriptions and initialization types for chausie mainboard"
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Change subject: drivers/intel/fsp2_0/include/fsp: fix fsp_header
......................................................................
Patch Set 9:
(1 comment)
File src/drivers/intel/fsp2_0/header_display.c:
https://review.coreboot.org/c/coreboot/+/58869/comment/c802d226_df67c17b
PS9, Line 11: int i;
> i'd use an unsigned int here, since it's always 0 or positive
I like to stick to K&R style where int is the default data type for things like 'for loops'.
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Change subject: drivers/i2c/designware/dw_i2c: return enum cb_err from dw_i2c_init
......................................................................
Patch Set 1: Code-Review+1
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Change subject: drivers/intel/fsp2_0/include/fsp: fix fsp_header
......................................................................
Patch Set 9:
(2 comments)
File src/drivers/intel/fsp2_0/header_display.c:
https://review.coreboot.org/c/coreboot/+/58869/comment/915b5fef_ed86a7f0
PS9, Line 11: int i;
i'd use an unsigned int here, since it's always 0 or positive
File src/drivers/intel/fsp2_0/include/fsp/info_header.h:
https://review.coreboot.org/c/coreboot/+/58869/comment/8a6fe162_55be270d
PS8, Line 22: char image_id[8];
> would be useful to add a comment to beware that this isn't a zero terminated string
Done
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Change subject: soc/intel/common: Define enum cpu_type type for core types
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/61459/comment/868c7dc3_a8af726e
PS3, Line 14: cpu_type
Hm, there is already an
`enum cpu_type`
that is in scope here.
Maybe this could be
`enum core_size`
or
`enum cpu_perf_type`
?
https://review.coreboot.org/c/coreboot/+/61459/comment/ae762588_02f535fb
PS3, Line 94: if (global_cpu_type[core_id])
`if (global_cpu_type[core_id] == CPU_TYPE_BIG)`
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Subrata Banik has uploaded a new patch set (#31) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/59638 )
Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
FSP 2.3 spec introduced FSP_NON_VOLATILE_STORAGE_HOB2 HOB version
for NV data storage. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated
from FSP 2.3 onwards and is maintained for backward compatibility only.
This patch implements the parsing method for
FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first
searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue
to search for FSP_NON_VOLATILE_STORAGE_HOB HOB.
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e
---
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/util.h
2 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/31
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/brya/var/vell: Enable SaGv
......................................................................
mb/google/brya/var/vell: Enable SaGv
This patch enables SaGv since somehow it was accidently removed
by commit a52b9c3.
BUG=b:208719081
TEST=FW_NAME=vell emerge-brya coreboot
Fixes:a52b9c3 ("mb/google/brya: Move gpio_pm settings for brya
variants to baseboards")
Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com>
Change-Id: Ideae3dbd9746590db104d93afadbd8d574298b83
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/61464/2
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Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
Patch Set 16:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/6610a480_4079549e
PS15, Line 240: its
> Yes, you are right, I will take care while rebasing
Ack
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