coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

1 participants
6716 discussions

Change in coreboot[master]: mb/google/brya/anahera: Swap TPM I2C with touchscreen I2C
by Nick Vaccaro (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Chen Wisley, Wisley Chen. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60432 ) Change subject: mb/google/brya/anahera: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bb1857b4c5b06ca4ad660bf73e0c4df9c376a58 Gerrit-Change-Number: 60432 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 20:14:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/include/lpc: add comment about RANGE_UNIT values
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60771 ) Change subject: soc/amd/common/block/include/lpc: add comment about RANGE_UNIT values ...................................................................... soc/amd/common/block/include/lpc: add comment about RANGE_UNIT values Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I22f3485ec81f76af7e0e96b7c1271d5ccf52e701 --- M src/soc/amd/common/block/include/amdblocks/lpc.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/60771/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 173cbd1..558b608 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -74,7 +74,7 @@ #define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ #define ROM_RANGE_WP BIT(10) #define ROM_RANGE_RP BIT(9) -#define RANGE_UNIT BIT(8) +#define RANGE_UNIT BIT(8) /* 0: 4kiB, 1: 64kiB */ #define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */ #define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n)) #define MAX_ROM_PROTECT_RANGES 4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22f3485ec81f76af7e0e96b7c1271d5ccf52e701 Gerrit-Change-Number: 60771 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/common/lpc/espi_util: move register definitions to header file
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60770 ) Change subject: soc/amd/common/lpc/espi_util: move register definitions to header file ...................................................................... soc/amd/common/lpc/espi_util: move register definitions to header file Define the register offsets and bits in a separate header file instead of in the middle of the .c file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25 --- A src/soc/amd/common/block/lpc/espi_def.h M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 56 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/60770/1 diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h new file mode 100644 index 0000000..a14f10f --- /dev/null +++ b/src/soc/amd/common/block/lpc/espi_def.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_ESPI_DEF_H +#define AMD_BLOCK_ESPI_DEF_H + +#define ESPI_DN_TX_HDR0 0x00 +#define ESPI_DN_TX_HDR1 0x04 +#define ESPI_DN_TX_HDR2 0x08 +#define ESPI_DN_TX_DATA 0x0c + +#define ESPI_MASTER_CAP 0x2c +#define ESPI_VW_MAX_SIZE_SHIFT 13 +#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) + +#define ESPI_GLOBAL_CONTROL_0 0x30 +#define ESPI_WAIT_CNT_SHIFT 24 +#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) +#define ESPI_WDG_CNT_SHIFT 8 +#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) +#define ESPI_AL_IDLE_TIMER_SHIFT 4 +#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) +#define ESPI_AL_STOP_EN (1 << 3) +#define ESPI_PR_CLKGAT_EN (1 << 2) +#define ESPI_WAIT_CHKEN (1 << 1) +#define ESPI_WDG_EN (1 << 0) + +#define ESPI_GLOBAL_CONTROL_1 0x34 +#define ESPI_RGCMD_INT_MAP_SHIFT 13 +#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_ERR_INT_MAP_SHIFT 8 +#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_SUB_DECODE_SLV_SHIFT 3 +#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) +#define ESPI_SUB_DECODE_EN (1 << 2) +#define ESPI_BUS_MASTER_EN (1 << 1) +#define ESPI_SW_RST (1 << 0) + +#define ESPI_SLAVE0_INT_EN 0x6c +#define ESPI_SLAVE0_INT_STS 0x70 +#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) +#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) +#define ESPI_STATUS_FATAL_ERROR (1 << 5) +#define ESPI_STATUS_NO_RESPONSE (1 << 4) +#define ESPI_STATUS_CRC_ERR (1 << 2) +#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) +#define ESPI_STATUS_BUS_ERROR (1 << 0) + +#define ESPI_RXVW_POLARITY 0xac + +#endif /* AMD_BLOCK_ESPI_DEF_H */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index f36f778..1e5b5d0 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -10,6 +10,8 @@ #include <timer.h> #include <types.h> +#include <espi_def.h> + static uintptr_t espi_bar; void espi_update_static_bar(uintptr_t bar) @@ -315,7 +317,6 @@ return CB_SUCCESS; } -#define ESPI_DN_TX_HDR0 0x00 enum espi_cmd_type { CMD_TYPE_SET_CONFIGURATION = 0, CMD_TYPE_GET_CONFIGURATION = 1, @@ -326,53 +327,6 @@ CMD_TYPE_FLASH = 7, }; -#define ESPI_DN_TX_HDR1 0x04 -#define ESPI_DN_TX_HDR2 0x08 -#define ESPI_DN_TX_DATA 0x0c - -#define ESPI_MASTER_CAP 0x2c -#define ESPI_VW_MAX_SIZE_SHIFT 13 -#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) - -#define ESPI_GLOBAL_CONTROL_0 0x30 -#define ESPI_WAIT_CNT_SHIFT 24 -#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) -#define ESPI_WDG_CNT_SHIFT 8 -#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) -#define ESPI_AL_IDLE_TIMER_SHIFT 4 -#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) -#define ESPI_AL_STOP_EN (1 << 3) -#define ESPI_PR_CLKGAT_EN (1 << 2) -#define ESPI_WAIT_CHKEN (1 << 1) -#define ESPI_WDG_EN (1 << 0) - -#define ESPI_GLOBAL_CONTROL_1 0x34 -#define ESPI_RGCMD_INT_MAP_SHIFT 13 -#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_ERR_INT_MAP_SHIFT 8 -#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_SUB_DECODE_SLV_SHIFT 3 -#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) -#define ESPI_SUB_DECODE_EN (1 << 2) -#define ESPI_BUS_MASTER_EN (1 << 1) -#define ESPI_SW_RST (1 << 0) - -#define ESPI_SLAVE0_INT_EN 0x6c -#define ESPI_SLAVE0_INT_STS 0x70 -#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) -#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) -#define ESPI_STATUS_FATAL_ERROR (1 << 5) -#define ESPI_STATUS_NO_RESPONSE (1 << 4) -#define ESPI_STATUS_CRC_ERR (1 << 2) -#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) -#define ESPI_STATUS_BUS_ERROR (1 << 0) - -#define ESPI_RXVW_POLARITY 0xac - #define ESPI_CMD_TIMEOUT_US 100 #define ESPI_CH_READY_TIMEOUT_US 10000 -- To view, visit https://review.coreboot.org/c/coreboot/+/60770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25 Gerrit-Change-Number: 60770 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya/{kano,taeko}: Change reset type of CPU PCIe vGPIOs
by Nick Vaccaro (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: David Wu, Tim Wawrzynczak, Kane Chen, Curtis Chen. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59762 ) Change subject: mb/google/brya/{kano,taeko}: Change reset type of CPU PCIe vGPIOs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59762/comment/420cdaad_d6d7b7cc PS1, Line 14: BUG ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I599b6b50f1a71923dd3acc9c16ef1d6b62c9f8fb Gerrit-Change-Number: 59762 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: YH Lin <yueherngl(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 20:03:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/taeko:Remove duplicate DB_SD fw_config fields.
by Nick Vaccaro (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: YH Lin, Joey Peng. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60409 ) Change subject: mb/google/brya/var/taeko:Remove duplicate DB_SD fw_config fields. ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7814c35f63fd6fa27195d448c4d51fc980aaa9c Gerrit-Change-Number: 60409 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 20:01:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: IASL: Ignore IASL's "Missing dependency" warning
by HAOUAS Elyes (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Michał Żygowski, Frans Hendriks, Tristan Corrick, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Piotr Król, Wim Vervoorn. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59880 ) Change subject: IASL: Ignore IASL's "Missing dependency" warning ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59880/comment/d2625fd8_a5d1e744 PS1, Line 16: > It’d be nice to only disable the warning for boards having the problem. so step back to patch set 5 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28b437194f08232727623009372327fec15215dd Gerrit-Change-Number: 59880 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth - Personal <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 20:00:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0
by 9elements QA (Code Review) 04 Jan '22

04 Jan '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60284 ) Change subject: mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0 ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/87724 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/87723 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87722 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/87721 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/87720 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/87719 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87718 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/87717 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/87716 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/87715 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/60284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67a0b282710031b927ce9022c7c535bd8d4ca1aa Gerrit-Change-Number: 60284 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 19:47:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/lpc/espi_util: handle espi_get_configuration error
by Raul Rangel (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60209 ) Change subject: soc/amd/common/lpc/espi_util: handle espi_get_configuration error ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9 Gerrit-Change-Number: 60209 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Jan 2022 19:44:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/espi: use lower case hex digits in definitions
by Raul Rangel (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60769 ) Change subject: soc/amd/common/block/espi: use lower case hex digits in definitions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0955db7afd101ab522845d5911ff971408e520e3 Gerrit-Change-Number: 60769 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Jan 2022 19:44:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/espi: use lower case hex digits in definitions
by Felix Held (Code Review) 04 Jan '22

04 Jan '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60769 ) Change subject: soc/amd/common/block/espi: use lower case hex digits in definitions ...................................................................... soc/amd/common/block/espi: use lower case hex digits in definitions coreboot uses lower case hex digits instead of upper case ones. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0955db7afd101ab522845d5911ff971408e520e3 --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/60769/1 diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index adb9a1d..4e8b898 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -21,7 +21,7 @@ #define ESPI_MMIO_BASE_OFFSET_REG0 0x50 #define ESPI_MMIO_BASE_OFFSET_REG1 0x54 #define ESPI_MMIO_BASE_OFFSET_REG2 0x58 -#define ESPI_MMIO_BASE_OFFSET_REG3 0x5C +#define ESPI_MMIO_BASE_OFFSET_REG3 0x5c #define ESPI_MMIO_OFFSET_SIZE_REG0 0x60 #define ESPI_MMIO_OFFSET_SIZE_REG1 0x64 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index d9b4715..f36f778 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -336,9 +336,9 @@ #define ESPI_GLOBAL_CONTROL_0 0x30 #define ESPI_WAIT_CNT_SHIFT 24 -#define ESPI_WAIT_CNT_MASK (0x3F << ESPI_WAIT_CNT_SHIFT) +#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) #define ESPI_WDG_CNT_SHIFT 8 -#define ESPI_WDG_CNT_MASK (0xFFFF << ESPI_WDG_CNT_SHIFT) +#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) #define ESPI_AL_IDLE_TIMER_SHIFT 4 #define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) #define ESPI_AL_STOP_EN (1 << 3) @@ -348,20 +348,20 @@ #define ESPI_GLOBAL_CONTROL_1 0x34 #define ESPI_RGCMD_INT_MAP_SHIFT 13 -#define ESPI_RGCMD_INT_MAP_MASK (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) #define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT_SMI (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) #define ESPI_ERR_INT_MAP_SHIFT 8 -#define ESPI_ERR_INT_MAP_MASK (0x1F << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) #define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT_SMI (0x1F << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) #define ESPI_SUB_DECODE_SLV_SHIFT 3 #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) #define ESPI_SUB_DECODE_EN (1 << 2) #define ESPI_BUS_MASTER_EN (1 << 1) #define ESPI_SW_RST (1 << 0) -#define ESPI_SLAVE0_INT_EN 0x6C +#define ESPI_SLAVE0_INT_EN 0x6c #define ESPI_SLAVE0_INT_STS 0x70 #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) -- To view, visit https://review.coreboot.org/c/coreboot/+/60769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0955db7afd101ab522845d5911ff971408e520e3 Gerrit-Change-Number: 60769 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2022