coreboot-gerrit January 2022

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Change in coreboot[master]: docker/Makefile: Use all instead of all_without_gdb
by Martin Roth (Code Review) 04 Jan '22

04 Jan '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60268 ) Change subject: docker/Makefile: Use all instead of all_without_gdb ...................................................................... docker/Makefile: Use all instead of all_without_gdb After removing GDB from crossgcc in commit f32eed16 (buildgcc: Remove GDB from crossgcc), there is no target named all_without_gdb anymore and we should always build crossgcc with target all. But in util/docker/Makefile, we still try to build crossgcc with target all_without_gdb as default and will cause a build failure. Set CROSSGCC_PARAM from all_without_gdb to all to fix this issue. Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Change-Id: I06c6d8e36dfd4e6a00ddec8b640b608ab1ba614c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60268 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M util/docker/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve Felix Singer: Looks good to me, but someone else must approve diff --git a/util/docker/Makefile b/util/docker/Makefile index 87e21be..cbe34f9 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -24,7 +24,7 @@ export DOCKER_CCACHE?=$(HOME)/.ccache # SDK architecture -export COREBOOT_CROSSGCC_PARAM?=all_without_gdb +export COREBOOT_CROSSGCC_PARAM?=all UID ?= $(shell id -u) GID ?= $(shell id -g) -- To view, visit https://review.coreboot.org/c/coreboot/+/60268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06c6d8e36dfd4e6a00ddec8b640b608ab1ba614c Gerrit-Change-Number: 60268 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: docker/Makefile: Use all instead of all_without_gdb
by Martin Roth (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Paul Menzel. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60268 ) Change subject: docker/Makefile: Use all instead of all_without_gdb ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06c6d8e36dfd4e6a00ddec8b640b608ab1ba614c Gerrit-Change-Number: 60268 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 21:08:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/apcb: Add apcb_v3_edit tool
by Rob Barnes (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Raul Rangel. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60281 ) Change subject: util/apcb: Add apcb_v3_edit tool ...................................................................... Patch Set 3: (5 comments) This change is ready for review. File util/apcb/apcb_v3_edit.py: https://review.coreboot.org/c/coreboot/+/60281/comment/8e938b9b_c24ecdf2 PS2, Line 73: open(args.apcb_in, 'rb') > ``` […] Done https://review.coreboot.org/c/coreboot/+/60281/comment/afc738cb_9f18b776 PS2, Line 77: C > Input APCB Done https://review.coreboot.org/c/coreboot/+/60281/comment/d0ff2690_1c0fa5d2 PS2, Line 81: fromhex > Need to check the hex argument? Are you suggesting to check that the hex byte is in range? As is, this will cause an ValueError and cause the build to fail. I can add a try catch and output and more informative error in this case. https://review.coreboot.org/c/coreboot/+/60281/comment/6b1ff0c1_dc747393 PS2, Line 81: open > `with open()` Done https://review.coreboot.org/c/coreboot/+/60281/comment/21d77b30_e1d79942 PS2, Line 82: ) > maybe print the file that failed? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9148977c415df41210a3a13a1cd9b3bc1504a480 Gerrit-Change-Number: 60281 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 21:06:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: guybrush: Inject SPDs into APCB
by Rob Barnes (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Martin Roth - Personal. Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60775 ) Change subject: guybrush: Inject SPDs into APCB ...................................................................... guybrush: Inject SPDs into APCB Inject SPDs into APCB at coreboot build time. BUG=b:209486191 BRANCH=None TEST=Boot guybrush and nipperkin with injected APCB Change-Id: Ib21085855324e0d473dd5e258f35a52bed326901 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M Makefile.inc M src/mainboard/google/guybrush/Makefile.inc 2 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/60775/1 diff --git a/Makefile.inc b/Makefile.inc index 090505e..cc7317d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -591,6 +591,8 @@ APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py +APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py + CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage FUTILITY?=$(objutil)/futility/futility diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index fa729fe..256849f 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -3,14 +3,6 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c -ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin),) -$(info APCB sources present.) -APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin -APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin -else -$(info APCB sources not found. Skipping APCB.) -endif - romstage-y += port_descriptors.c romstage-y += romstage.c @@ -25,8 +17,13 @@ subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR) - CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include LIB_SPD_DEPS = $(SPD_SOURCES) + +APCB_SOURCES = $(obj)/APCB_CZN_D4.gen +APCB_SOURCES_RECOVERY = $(obj)/APCB_CZN_D4.gen + +$(obj)/APCB_CZN_D4.gen: $(SPD_SOURCES) $(APCB_V3_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin + $(APCB_V3_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin $(obj)/APCB_CZN_D4.gen --spd_sources $(SPD_SOURCES) -- To view, visit https://review.coreboot.org/c/coreboot/+/60775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib21085855324e0d473dd5e258f35a52bed326901 Gerrit-Change-Number: 60775 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Martin Roth - Personal <martinroth(a)google.com> Gerrit-Attention: Martin Roth - Personal <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/gpio: Rework PAD config macro to add lock support
by Subrata Banik (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60774 to look at the new patch set (#2). Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support ...................................................................... soc/intel/common/gpio: Rework PAD config macro to add lock support This patch creates new GPIO PAD configuration macros that would help toperform GPIO pad configuration and pad lock configuration as well. Lists of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK Mainboard users can use the above macros to lock the PAD after configuration. So far on IA chipset. the default GPIO pad lock configuration reset type is POWERGOOD hence, its recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type as same as lock configuration reset type to avoid GPP reset value misconfiguration issue. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 3 files changed, 79 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60774/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Gerrit-Change-Number: 60774 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/gpio: Rework PAD config macro to add lock support
by build bot (Jenkins) (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60774 ) Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/include/intelblocks/gpio_defs.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137279): https://review.coreboot.org/c/coreboot/+/60774/comment/043f62b4_cca2bfe9 PS1, Line 315: #define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, action) \ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137279): https://review.coreboot.org/c/coreboot/+/60774/comment/cab32989_4d7819ec PS1, Line 332: PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE), \ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/60774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Gerrit-Change-Number: 60774 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 04 Jan 2022 20:45:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/gpio: Rework PAD config macro to add lock support
by Subrata Banik (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60774 ) Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support ...................................................................... soc/intel/common/gpio: Rework PAD config macro to add lock support This patch creates new GPIO PAD configuration macros that would help toperform GPIO pad configuration and pad lock configuration as well. Lists of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK Mainboard users can use the above macros to lock the PAD after configuration. So far on IA chipset. the default GPIO pad lock configuration reset type is POWERGOOD hence, its recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type as same as lock configuration reset type to avoid GPP reset value misconfiguration issue. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 3 files changed, 79 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60774/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 419c77e..3a6f7b7 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -341,6 +341,8 @@ gpio_configure_owner(cfg, comm); gpi_enable_smi(cfg, comm); gpi_enable_nmi(cfg, comm); + if (cfg->action) + gpio_lock_pad(cfg->pad, cfg->action); } void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 700b975..5342f76 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -65,10 +65,18 @@ typedef uint32_t gpio_t; +enum gpio_lock_action { + GPIO_UNLOCK = 0x0, + GPIO_LOCK_CONFIG = 0x1, + GPIO_LOCK_TX = 0x2, + GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX, +}; + struct pad_config { gpio_t pad;/* offset of pad within community */ uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];/* Pad config data corresponding to DW0, DW1,.... */ + enum gpio_lock_action action; /* Pad lock configuration */ }; /* @@ -199,12 +207,6 @@ */ void *gpio_dwx_address(const gpio_t pad); -enum gpio_lock_action { - GPIO_LOCK_CONFIG = 0x1, - GPIO_LOCK_TX = 0x2, - GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX, -}; - struct gpio_lock_config { gpio_t pad; enum gpio_lock_action action; diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index d3249bc..53b2f0e 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -129,6 +129,7 @@ #define PAD_IRQ_ROUTE(value) PAD_CFG0_ROUTE_##value #define PAD_TRIG(value) PAD_CFG0_TRIG_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value +#define PAD_LOCK(value) GPIO_##value /* Disable the input/output buffer of the pad */ #define PAD_CFG0_BUF_NO_DISABLE (0) @@ -165,6 +166,15 @@ .pad = __pad, \ .pad_config[0] = __config0, \ .pad_config[1] = __config1, \ + .action = PAD_LOCK(UNLOCK), \ + } + +#define _PAD_CFG_STRUCT_LOCK(__pad, __config0, __config1, __action) \ + { \ + .pad = __pad, \ + .pad_config[0] = __config0, \ + .pad_config[1] = __config1, \ + .action = __action, \ } #if GPIO_NUM_PAD_CFG_REGS > 2 @@ -174,6 +184,7 @@ .pad_config[0] = __config0, \ .pad_config[1] = __config1, \ .pad_config[2] = __config2, \ + .action = PAD_LOCK(UNLOCK), \ } #else #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ @@ -186,6 +197,13 @@ PAD_RESET(rst) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) +/* Native function configuration with lock */ +#define PAD_CFG_NF_LOCK(pad, pull, func, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_RESET(PWROK) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE), \ + PAD_LOCK(action)) + #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS @@ -230,6 +248,14 @@ PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) +/* General purpose output with lock, no pullup/down. */ +#define PAD_CFG_GPO_LOCK(pad, val, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), \ + PAD_LOCK(action)) + /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ @@ -258,6 +284,13 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +/* General purpose input with lock */ +#define PAD_CFG_GPI_LOCK(pad, pull, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + #define PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \ @@ -279,12 +312,26 @@ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), \ + PAD_LOCK(action)) + #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_GPIO_DRIVER_LOCK(pad, pull, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ + PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ @@ -300,6 +347,10 @@ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) +/* GPIO Interrupt with lock */ +#define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, action) \ + PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, action) + /* * No Connect configuration for unconnected or unused pad. * Both TX and RX are disabled. RX disabling is done to avoid unnecessary @@ -319,6 +370,14 @@ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) +/* General purpose input with lock, routed to APIC */ +#define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + /* General purpose input, routed to APIC - with IOStandby Config*/ #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ @@ -406,9 +465,19 @@ PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, rst, trig, inv, route1, route2, action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \ + PAD_LOCK(action)) + #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) +#define PAD_CFG_GPI_IRQ_WAKE_LOCK(pad, pull, trig, inv, action) \ + PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, PWROK, trig, inv, IOAPIC, SCI, action) + #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ #endif /* _SOC_BLOCK_GPIO_DEFS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Gerrit-Change-Number: 60774 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/gpio: Modify pad_config.pad type from `int` to 'gpio_t'
by Subrata Banik (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60773 ) Change subject: soc/intel/common/gpio: Modify pad_config.pad type from `int` to 'gpio_t' ...................................................................... soc/intel/common/gpio: Modify pad_config.pad type from `int` to 'gpio_t' This patch modifies struct pad_config.pad type from `int` to 'gpio_t' as pad offset inside GPIO community is unsigned type and also to maintain parity with `struct gpio_lock_config.pad` type. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1 --- M src/soc/intel/common/block/include/intelblocks/gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/60773/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 995c786..700b975 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -66,7 +66,7 @@ typedef uint32_t gpio_t; struct pad_config { - int pad;/* offset of pad within community */ + gpio_t pad;/* offset of pad within community */ uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];/* Pad config data corresponding to DW0, DW1,.... */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/60773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1 Gerrit-Change-Number: 60773 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/gpio: Rename struct gpio_lock_config.gpio to .pad
by Subrata Banik (Code Review) 04 Jan '22

04 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60772 ) Change subject: soc/intel/common/gpio: Rename struct gpio_lock_config.gpio to .pad ...................................................................... soc/intel/common/gpio: Rename struct gpio_lock_config.gpio to .pad This patch renames struct gpio_lock_config variable `gpio` to `pad`, to represent the pad offset within the GPIO community. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6bed99c401435c96c9543f99406a934d7141c575 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/60772/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index ce23a2e..419c77e 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -500,7 +500,7 @@ for (int x = 0; x < count; x++) { int err; - pad = pad_list[x].gpio; + pad = pad_list[x].pad; action = pad_list[x].action; if (!(action & GPIO_LOCK_FULL)) { @@ -555,7 +555,7 @@ int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action) { const struct gpio_lock_config pads = { - .gpio = pad, + .pad = pad, .action = action }; diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 91f9abe..995c786 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -206,7 +206,7 @@ }; struct gpio_lock_config { - gpio_t gpio; + gpio_t pad; enum gpio_lock_action action; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/60772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bed99c401435c96c9543f99406a934d7141c575 Gerrit-Change-Number: 60772 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/anahera: Swap TPM I2C with touchscreen I2C
by Nick Vaccaro (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Chen Wisley, Wisley Chen. Nick Vaccaro has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/60432 ) Change subject: mb/google/brya/anahera: Swap TPM I2C with touchscreen I2C ...................................................................... Removed Code-Review+2 by Nick Vaccaro <nvaccaro(a)google.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/60432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bb1857b4c5b06ca4ad660bf73e0c4df9c376a58 Gerrit-Change-Number: 60432 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: deleteVote

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