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Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
Patch Set 29:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60104/comment/de868d44_d5746152
PS27, Line 2: Ariel_Fang
> Please change to Ariel Fang: […]
done
https://review.coreboot.org/c/coreboot/+/60104/comment/bc2ee4cc_6763f61b
PS27, Line 10: so this CL programs them as PAD_NC
> Please clarify by adding something like: […]
done
https://review.coreboot.org/c/coreboot/+/60104/comment/7a61124d_821f3fd0
PS27, Line 19: Ariel_Fang
> Ditto.
done
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60104
to look at the new patch set (#29).
Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
mb/google/brya/var/primus: Fix some GPIO programming
After checking them against schematics, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B2 => non-use
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use (Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot
Signed-off-by: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/29
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Change subject: mb/google/brya/var/brask: Change TPM I2C to I2C1
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60439/comment/432ec5bf_3d118466
PS4, Line 91: .rise_time_ns = 600,
: .fall_time_ns = 400,
: .data_hold_time_ns = 50,
> I imagine these were borrowed from brya?
Yes, this setting is from the brya. The brask is forked from the brya, so we can apply the same setting.
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60270
to look at the new patch set (#3).
Change subject: mb/google/brya/var/gimble: Decrease touchscreen T3 timing to 200ms
......................................................................
mb/google/brya/var/gimble: Decrease touchscreen T3 timing to 200ms
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times are greater than 500ms, which is the spec for Chromebooks. The actual kernel timing has been measured, and given the ACPI delay after deasserting reset in addition to
the delay until the kernel driver accesses the device, delaying
only 200ms in the ACPI method is also sufficient to meet the 300ms
requirement.
BUG=b:210772498
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.
Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Change-Id: I4bb4eda09686cb59b6e19c741aa2b78d84332d2a
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/60270/3
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Change subject: Add console deinit API, use in SMM handler
......................................................................
Patch Set 11:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56386/comment/75f82282_4ce935a9
PS11, Line 14: on an OCP Delta Lake server: uart8250_init disables interrupts because it
> I agree cleaning up after the uart output is useful for debugging the SMM handlers. […]
I think adding for the 8250 drives is sufficient.
File src/drivers/uart/sifive.c:
https://review.coreboot.org/c/coreboot/+/56386/comment/b8788414_8a898acf
PS11, Line 58: /* TODO */
> If this is for SMM, do we really need an implementation for the sifive UART?
Yes, if there is a system somewhere that uses sifive and runtime SMI's.
File src/drivers/uart/uart8250io.c:
https://review.coreboot.org/c/coreboot/+/56386/comment/146ba8e2_079f02d6
PS11, Line 58: static struct uart8250_state s_uart8250_state;
> Can this be implemented without a static global variable?
Possibly. Do you have another recommendation for saving the state?
https://review.coreboot.org/c/coreboot/+/56386/comment/844875ae_158a82d9
PS11, Line 62: /* Save previous state for restoring later. */
: s_uart8250_state.IER = inb(base_port + UART8250_IER);
: s_uart8250_state.FCR = inb(base_port + UART8250_FCR);
: s_uart8250_state.MCR = inb(base_port + UART8250_MCR);
: s_uart8250_state.LCR = inb(base_port + UART8250_LCR);
: s_uart8250_state.DLL = inb(base_port + UART8250_DLL);
: s_uart8250_state.DLM = inb(base_port + UART8250_DLM);
:
> If this is only needed by SMM, could we move this into a separate function that is called before uar […]
This can be done but then we would need to create another layer of API's to get to the correct console uart. How about if we surrounded this code with a CONFIG_DEBUG_SMI?
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60104
to look at the new patch set (#28).
Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
mb/google/brya/var/primus: Fix some GPIO programming
During the initial review, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B2 => non-use
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use (Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot
Signed-off-by: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/28
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Change subject: mb/google/brya/anahera{4es}: Correct SSD power sequence
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60434/comment/ac2c649f_43a7c38f
PS3, Line 7: anahera
> Just so it's clear this applies to both: […]
Done
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Change subject: mb/google/brya/anahera{4es}: Correct SSD power sequence
......................................................................
mb/google/brya/anahera{4es}: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:213021171
TEST=FW_NAME=redrix emerge-brya coreboot
Change-Id: I66345d985f4db4f13b23c0a21c179835908b6574
Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anahera/Makefile.inc
M src/mainboard/google/brya/variants/anahera/gpio.c
M src/mainboard/google/brya/variants/anahera4es/Makefile.inc
M src/mainboard/google/brya/variants/anahera4es/gpio.c
4 files changed, 36 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/60434/4
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