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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/brya/var/redrix: Enable MKBP wake
......................................................................
mb/google/brya/var/redrix: Enable MKBP wake
To timely update stylus charging status (b:206012072), PCHG device
events have been moved to MKBP. This patch registers the MKPB host
event as a wake-up signal to match the change.
EC filters other EC_MKBP_EVENT_* events (chromium:3413180).
BUG=b:205675485,b:206012072
Cq-Depend: chromium:3413180
Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Change-Id: Ie4536b2c0ccc37f92dfa940c5a5712340a32c82c
---
M src/mainboard/google/brya/variants/redrix/include/variant/ec.h
1 file changed, 9 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/61383/2
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Change subject: soc/intel/graphics: Add override api for graphics_get_memory_base()
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/61389/comment/403f51c1_f2f8ec49
PS2, Line 17: #include <soc/graphic.h>
I guess you defines graphics_memory_base_override in this header file.
Can you move definition to common header(intelblocks/graphics.h)?
As you can see existing builds are failed during including the header file which does not exist in previous platforms.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61377 )
Change subject: soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-M
......................................................................
soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-M
Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master]
updated the FSP binaries/headers for Comet Lake, which included a change
moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing
UDP in FSP-S was left in and deprecated, which allowed the change to go
unnoticed until it was discovered that hotplug wasn't working.
Since other related platforms (WHL, CFL) share the SoC code but use
different FSP packages, add the setting of the PcieRpHotPlug UPD to
romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'.
Test: build/boot Purism Librem 14, verify WiFi killswitch operates
as expected / WiFi is re-enabled when turning switch to on position.
Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Paul Menzel: Looks good to me, but someone else must approve
Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 8cb6c92..0b63bd5 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -59,6 +59,7 @@
m_cfg->EnableC6Dram = config->enable_c6dram;
#if CONFIG(SOC_INTEL_COMETLAKE)
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+ memcpy(tconfig->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(tconfig->PcieRpHotPlug));
#else
m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
#endif
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John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61283 )
Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61283/comment/d1f89ae5_fdd58be8
PS3, Line 10: p2sb2
> > > In your example, would the 2nd P2SB for PlatformX and PlatformY have anything in common other th […]
Since there are concerns to use either the ambiguous p2sb2 or another term for 2nd p2sb, I am dropping the p2sb2 and will add xxx_p2sb back once restriction is lifted.
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Change subject: mb/google/brya: Add GPIO table for nissa
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> compiler is complaining about GPP_I5, have the GPIO I group changes landed yet?
Not yet CB:61106
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Hello build bot (Jenkins), Wonkyu Kim, Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61283
to look at the new patch set (#5).
Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
soc/intel/common: Add the Primary to Sideband bridge library
New platforms have additional Primary to Sideband bridge besides the PCH
P2SB. This change puts the common functions into the P2SB library.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao(a)intel.com>
Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55
---
M src/soc/intel/common/block/include/intelblocks/p2sb.h
A src/soc/intel/common/block/include/intelblocks/p2sblib.h
M src/soc/intel/common/block/p2sb/Makefile.inc
M src/soc/intel/common/block/p2sb/p2sb.c
A src/soc/intel/common/block/p2sb/p2sblib.c
5 files changed, 85 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/61283/5
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59256 )
Change subject: util: Add coreboot-configurator
......................................................................
Patch Set 17: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59256/comment/14c373f0_0c336763
PS15, Line 7: util: Add coreboot-configurator
> I think that discussion was on the first patch set that I scrapped - but yes, short version, coreboo […]
I agree.
Patchset:
PS17:
Let's get the initial merge done and then anything else can be added in follow-on patches.
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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61091 )
Change subject: soc/amd/sabrina/fsp_m_params: drop sata_enable UPD write
......................................................................
Patch Set 4: Code-Review+1
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61349 )
Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
> Done
"cbfs_file + filename + metadata" -- Does this mean if the filename was really long this would all fail?
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