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Change subject: soc/intel/graphics: Add override api for graphics_get_memory_base()
......................................................................
soc/intel/graphics: Add override api for graphics_get_memory_base()
graphic memory may vary by every platfrom.
override api will be flexible for each platform to override if require.
TEST= apply platform soc folder to test
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/Kconfig.common
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/4
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61408 )
Change subject: mb/purism/librem_skl: disable HECI PCI device
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61408/comment/22d690ef_98e6ac13
PS1, Line 10: a 15s timeout delay when booting.
mention you are disabling it via OOB mechanisms, herefore it shouldn't have the HECI bus initialized?
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Change subject: vc/amd/agesa: fix out-of-bounds read
......................................................................
Patch Set 6: Code-Review+2
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Change subject: vc/amd/agesa: fix out-of-bounds read
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58803/comment/c898d39f_4ee7ef90
PS5, Line 9: Fix the out-of-bounds read issue found by Coverity.
> would be good to add the coverity bug id in the commit message. https://review.coreboot. […]
Done
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I'd like you to reexamine a change. Please visit
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Change subject: vc/amd/agesa: fix out-of-bounds read
......................................................................
vc/amd/agesa: fix out-of-bounds read
Fix the out-of-bounds read issue found by Coverity.
TEST=none
Signed-off-by: Jason Nien <finaljason(a)gmail.com>
Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509
Reported-by: Coverity (CID:1376956)
---
M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/58803/6
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/sabrina: add additional UART controllers
......................................................................
soc/amd/sabrina: add additional UART controllers
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23
---
M src/soc/amd/sabrina/Kconfig
M src/soc/amd/sabrina/acpi/mmio.asl
M src/soc/amd/sabrina/aoac.c
M src/soc/amd/sabrina/chip.c
M src/soc/amd/sabrina/chipset.cb
M src/soc/amd/sabrina/include/soc/uart.h
M src/soc/amd/sabrina/uart.c
7 files changed, 132 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61086/5
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Change subject: soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs
......................................................................
soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs
Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
---
M src/soc/amd/sabrina/acpi/pci_int_defs.asl
M src/soc/amd/sabrina/fch.c
M src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h
3 files changed, 12 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/61083/4
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Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
> "cbfs_file + filename + metadata" -- Does this mean if the filename was really long this would all f […]
Yes, since there isn't any metadata AFAIK, the name could be increased by somewhere in the range of 20 to 30 characters before it becomes an issue. Ideally, it would be nice to calculate the position directly instead of using a hard-coded value. However, my understanding of how the makefile operates is that these variables end up expanded at the top-level and not as part of a make target, preventing them from having access to all the information needed to precisely compute the position.
Adding in basic checks to fail the build if sizeof(struct cbfs_file) + len(filename) exceeds the available space would be simple, however that wouldn't account for any metadata being added at a later date. Though it should be possible to add a stage after the image is built that examines the image and fails if 64 bytes wasn't enough.
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Change subject: mb/google/brya/var/redrix: Enable MKBP wake
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61383/comment/9b8714ae_9d8d3912
PS1, Line 13: Cq-Depend: chromium:3413180
> Must go in the last "paragraph"
Done
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