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Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS1:
> Which cbfs header exactly, cbfs_file? 0x40 seems like a magic number here. […]
Done
File src/soc/amd/cezanne/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61349/comment/735312a9_b7f2fa07
PS3, Line 281: #Ensure this ends up at the beginning of the FW_MAIN_A fmap region, 0x40 accounts for the header size
> nit: Space after #.
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61349
to look at the new patch set (#4).
Change subject: soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
soc/amd/cezanne: Fix incorrect values of CBFS amdfw position makefile variables
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image.
BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by CBFSPRINT during the build
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
---
M src/soc/amd/cezanne/Makefile.inc
1 file changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61349/4
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61023 )
Change subject: Revert "mb/google/brya/var/brask: Configure the ISOLATE pin of LAN"
......................................................................
Revert "mb/google/brya/var/brask: Configure the ISOLATE pin of LAN"
This reverts commit 2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8.
According to the latest schematics, Brask supports D3-Hot for RTL8125
and does not need to operate the ISOLATE pin.
BUG=b:193750191
BRANCH=None
TEST=emerge-brask coreboot chromeos-bootimage
Test with command suspend_stress_test
Change-Id: Ica6bfb810887861f6b17ff527373824547e2406c
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61023
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/mainboard/google/brya/variants/brask/overridetree.cb
1 file changed, 0 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index b9c8edb..3aeca90 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -81,10 +81,6 @@
end
device ref pcie_rp7 on
chip drivers/net
- register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)"
- register "stop_delay_ms" = "12" # NIC needs time to quiesce
- register "stop_off_delay_ms" = "1"
- register "has_power_resource" = "1"
register "wake" = "GPE0_DW0_07"
register "led_feature" = "0xe0"
register "customized_led0" = "0x23f"
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Change subject: soc/intel/common/cse: skip heci_init() if HECI1 is disabled
......................................................................
Patch Set 2: Code-Review+2
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Change subject: util/chromeos: Update extract_blobs script
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
Patchset:
PS4:
Still some shellcheck issues, but those can be fixed in a follow-on patch if you want. This is a big improvement.
File util/chromeos/extract_blobs.sh:
https://review.coreboot.org/c/coreboot/+/59266/comment/4edf8a5b_477499fe
PS3, Line 11: DIR=$(basename $IMAGE)
> I'm creating a directory with '-blobs' appended to the input filename less the extension (bios. […]
Adding the comment should address the confusion when I first looked at it. Thanks.
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Change subject: drivers/intel/usb4/retimer: Use usb4_retimer_scope replace dev path
......................................................................
Patch Set 9: Code-Review+2
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58869 )
Change subject: drivers/intel/fsp2_0/include/fsp: fix fsp_header
......................................................................
Patch Set 7:
(1 comment)
File src/drivers/intel/fsp2_0/include/fsp/info_header.h:
https://review.coreboot.org/c/coreboot/+/58869/comment/70284642_6b883750
PS7, Line 30: temp
consider adding `fsp_` prefix for all entry APIs just to maintain the parity. Example line #33, #35
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61338 )
Change subject: mb/google/brya/var/kano: Reduce reset delay time to 20ms for ELAN TS
......................................................................
mb/google/brya/var/kano: Reduce reset delay time to 20ms for ELAN TS
Set register "reset_delay_ms" to 20 to reduce power resume time.
BUG=b:204009580
TEST=tested on kano
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: Ib0695edd7c342c65df9138b1590281c5f442769b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61338
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/brya/variants/kano/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index 4a49aa7..c3b47fb 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -420,7 +420,7 @@
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
- register "generic.reset_delay_ms" = "300"
+ register "generic.reset_delay_ms" = "20"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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