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Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Removed Code-Review+2 by Wonkyu Kim <wonkyu.kim(a)intel.com>
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Change subject: soc/intel/common: Add the Primary to Sideband bridge library
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
File src/soc/intel/common/block/include/intelblocks/p2sb.h:
https://review.coreboot.org/c/coreboot/+/61283/comment/55c0e6ad_4ca0122a
PS5, Line 46:
Remove blank line
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61388 )
Change subject: mb/google/brya: Add custom PLD fields to device tree
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/google/brya/variants/brya0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/61388/comment/629b35d4_f65745e8
PS6, Line 658: 1"
`PLD_HORIZONTAL_POSITION_CENTER`
https://review.coreboot.org/c/coreboot/+/61388/comment/3dd68e2d_1738e694
PS6, Line 655: register "use_custom_pld" = "true"
: register "custom_pld.visible" = "true"
: register "custom_pld.panel" = "PLD_PANEL_LEFT"
: register "custom_pld.horizontal_position" = "1"
: register "custom_pld.shape" = "PLD_SHAPE_OVAL"
: register "custom_pld.group" = "ACPI_PLD_GROUP(1, 1)"
We can clean up some of the wordiness like so:
```
register "use_custom_pld" = "true"
register "custom_pld" = "{
.visible = true,
.panel = PLD_PANEL_LEFT,
.horizontal_position = PLD_HORIZONTAL_POSITION_CENTER,
.shape = PLD_SHAPE_OVAL,
.group = ACPI_PLD_GROUP(1, 1)}"
```
it will make all of them a little less cluttered 👍
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Change subject: mb/purism/librem_skl: disable HECI PCI device
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61408/comment/f8079155_4410b197
PS1, Line 10: a 15s timeout delay when booting.
> mention you are disabling it via OOB mechanisms, herefore it shouldn't have the HECI bus initialized […]
Done
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/purism/librem_skl: disable HECI PCI device
......................................................................
mb/purism/librem_skl: disable HECI PCI device
As all librem_skl devices ship with the ME disabled via
HAP bit and ME firmware "neutralized" via me_cleaner,
the HECI1 PCI device should be marked off/disabled to
ensure that heci_init()/heci_reset() will not cause
a 15s timeout delay when booting.
Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
---
M src/mainboard/purism/librem_skl/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/61408/2
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Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
......................................................................
Patch Set 15:
(2 comments)
Patchset:
PS15:
Sridhar, would you mind adding an SSDT dump of CPPC to the bug, thanks!
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/59359/comment/49e085f5_9529f3f8
PS15, Line 108: 0
> This is expected to be 0. […]
Exactly, instead of writing out the same data N times (once for each core), it is written out once (core 0), and the other cores refer back to that info
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Change subject: soc/intel/graphics: Add override api for graphics_get_memory_base()
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/61389/comment/d55570c6_7e283638
PS2, Line 17: #include <soc/graphic.h>
> I guess you defines graphics_memory_base_override in this header file. […]
Thanks for point failure out. Correct it and updated.
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Change subject: mb/google/brya/var/redrix: Enable MKBP wake
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/brya/variants/redrix/include/variant/ec.h:
https://review.coreboot.org/c/coreboot/+/61383/comment/b4f296ad_3b61c53b
PS2, Line 14: EC_HOST_EVENT_USB_MUX
We should ensure that all brya devices have the same policies on wake (modulo exceptions like PCHG). Right now we have this as an S0ix-only wake in the brya baseboard, so this should probably be taken out here, and if the baseboard needs to be updated, then update it there.
https://review.coreboot.org/c/coreboot/+/61383/comment/ab5f026c_59271803
PS2, Line 21: EC_HOST_EVENT_MKBP
nit: this is redundant, it's already contained in `MAINBOARD_EC_S3_WAKE_EVENTS`
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Hello Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61389
to look at the new patch set (#5).
Change subject: soc/intel/graphics: Add override api for graphics_get_memory_base()
......................................................................
soc/intel/graphics: Add override api for graphics_get_memory_base()
graphic memory may vary by every platfrom.
override api will be flexible for each platform to override if require.
TEST= apply platform soc folder to test
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/Kconfig.common
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/include/intelblocks/graphics.h
3 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/5
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