Attention is currently required from: Shelley Chen, Julius Werner.
Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56901 )
Change subject: trogdor: Fix "TPM interrupt" lb_gpio to be ACTIVE_HIGH
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Pardon my ignorance, but what exactly makes this a "latched" GPIO? Is it because it's a GPIO that's exposed from coreboot to depthcharge and thus virtualized? If so, why would the "GPIO_AP_EC_INT" right above it be any different?
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Change subject: soc/amd/common: Show current SPI speeds and modes
......................................................................
Patch Set 1:
(8 comments)
File src/soc/amd/common/block/include/amdblocks/spi.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/da3548e1_8e873a3d
PS1, Line 38: #define DECODE_SPI_READ_MODE(x) DECODE_SPI_MODE_UPPER_BITS(x) | \
Macros with complex values should be enclosed in parentheses
File src/soc/amd/common/block/spi/fch_spi.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/4c8b9a81_bf7918ab
PS1, Line 40: printk(BIOS_DEBUG,"SPI normal read speed: %s\n",
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/88f5de34_2fae6e4f
PS1, Line 42: printk(BIOS_DEBUG,"SPI fast read speed: %s\n",
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/ea0f1b96_b98d5132
PS1, Line 44: printk(BIOS_DEBUG,"SPI alt read speed: %s\n",
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/5bdecaee_aed3d875
PS1, Line 46: printk(BIOS_DEBUG,"SPI TPM read speed: %s\n",
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/9c23046e_604f9a9b
PS1, Line 48: printk(BIOS_DEBUG,"SPI100: %s\n",spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ?
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/fb55a103_e346b904
PS1, Line 48: printk(BIOS_DEBUG,"SPI100: %s\n",spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ?
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126164):
https://review.coreboot.org/c/coreboot/+/56960/comment/e9a681ef_0b458f32
PS1, Line 50: printk(BIOS_DEBUG,"SPI Read Mode: %s\n",
space required after that ',' (ctx:VxV)
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John Zhao has uploaded a new patch set (#2) to the change originally created by Brandon Breitenstein. ( https://review.coreboot.org/c/coreboot/+/55771 )
Change subject: mb/intel/adlrvp: Update mainboard properties for BB retimer FW upgrade
......................................................................
mb/intel/adlrvp: Update mainboard properties for BB retimer FW upgrade
This change updates the mainboard with the DFp numbers and power_gpio for each DFP.
BUG=none
TEST=verified Retimer device coming up for upgrade
Change-Id: Ib20f0681313b044f627028f559ec69f690dfae46
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/devicetree.cb
2 files changed, 19 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/55771/2
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: mb/(amd,google): Update SPI Kconfig settings based on devicetree
......................................................................
mb/(amd,google): Update SPI Kconfig settings based on devicetree
This takes the devicetree SPI settings and moves them into Kconfig.
BUG=b:195943311
TEST=boot guybrush & majolica and verify spi settings.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed
---
M src/mainboard/amd/bilby/Kconfig
M src/mainboard/amd/majolica/Kconfig
M src/mainboard/amd/mandolin/Kconfig
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/zork/Kconfig
5 files changed, 76 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/56885/3
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Martin Roth has uploaded a new patch set (#2) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/56815 )
Change subject: mb/amd/majolica/Kconfig: add EFS SPI settings
......................................................................
mb/amd/majolica/Kconfig: add EFS SPI settings
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100
case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to
Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config
for the EM100 emulator case that has limited SPI frequency support.
Tested on Majolica by Martin.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869
---
M src/mainboard/amd/majolica/Kconfig
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/56815/2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56884
to look at the new patch set (#3).
Change subject: soc/amd/common/block/spi: Add SPI config to Kconfig
......................................................................
soc/amd/common/block/spi: Add SPI config to Kconfig
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=boot majolica & guybrush, verify spi settings
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
---
M src/soc/amd/common/block/spi/Kconfig
1 file changed, 44 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56884/3
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