coreboot-gerrit August 2021

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Change in coreboot[master]: tests: Add lib/cbfs-verification-test test case
by Paul Fagerburg (Code Review) 13 Aug '21

13 Aug '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56601 ) Change subject: tests: Add lib/cbfs-verification-test test case ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330 Gerrit-Change-Number: 56601 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 12 Aug 2021 22:04:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1
by Matthew Blecker (Code Review) 13 Aug '21

13 Aug '21

Attention is currently required from: Furquan Shaikh, Caveh Jalali, Paul Menzel. Matthew Blecker has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56928 ) Change subject: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > On coreboot. […] Ah, sounds good. I had read the "Submitting a patch" doc (https://doc.coreboot.org/tutorial/part2.html) but missed the existence of the Gerrit Guidelines. -- To view, visit https://review.coreboot.org/c/coreboot/+/56928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Gerrit-Change-Number: 56928 Gerrit-PatchSet: 5 Gerrit-Owner: Matthew Blecker <matthewb(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 12 Aug 2021 21:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Matthew Blecker <matthewb(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 13 Aug '21

13 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52846 ) Change subject: soc/intel/alderlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/alderlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 5 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index cb4552d..3accdbb 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -401,17 +401,11 @@ const struct soc_intel_alderlake_config *config) { /* Chipset Lockdown */ - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - s_cfg->PchLockDownGlobalSmi = 0; - s_cfg->PchLockDownBiosInterface = 0; - s_cfg->PchUnlockGpioPads = 1; - s_cfg->RtcMemoryLock = 0; - } else { - s_cfg->PchLockDownGlobalSmi = 1; - s_cfg->PchLockDownBiosInterface = 1; - s_cfg->PchUnlockGpioPads = 0; - s_cfg->RtcMemoryLock = 1; - } + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; + s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; + s_cfg->PchUnlockGpioPads = !lockdown_by_fsp; + s_cfg->RtcMemoryLock = lockdown_by_fsp; /* coreboot will send EOP before loading payload */ s_cfg->EndOfPostMessage = EOP_DISABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/52846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Gerrit-Change-Number: 52846 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 13 Aug '21

13 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52845 ) Change subject: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/jasperlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52845 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 5 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index d68494f..bb41b28 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -70,17 +70,11 @@ params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); /* Chipset Lockdown */ - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - params->PchLockDownGlobalSmi = 0; - params->PchLockDownBiosInterface = 0; - params->PchUnlockGpioPads = 1; - params->RtcMemoryLock = 0; - } else { - params->PchLockDownGlobalSmi = 1; - params->PchLockDownBiosInterface = 1; - params->PchUnlockGpioPads = 0; - params->RtcMemoryLock = 1; - } + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + params->PchLockDownGlobalSmi = lockdown_by_fsp; + params->PchLockDownBiosInterface = lockdown_by_fsp; + params->PchUnlockGpioPads = !lockdown_by_fsp; + params->RtcMemoryLock = lockdown_by_fsp; /* coreboot will send EOP before loading payload */ params->EndOfPostMessage = EOP_DISABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/52845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Gerrit-Change-Number: 52845 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 13 Aug '21

13 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52844 ) Change subject: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/tigerlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52844 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 5 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index c788fc4..a3ce68a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -393,17 +393,11 @@ params->DisableTccoldOnUsbConnected = 1; /* Chipset Lockdown */ - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - params->PchLockDownGlobalSmi = 0; - params->PchLockDownBiosInterface = 0; - params->PchUnlockGpioPads = 1; - params->RtcMemoryLock = 0; - } else { - params->PchLockDownGlobalSmi = 1; - params->PchLockDownBiosInterface = 1; - params->PchUnlockGpioPads = 0; - params->RtcMemoryLock = 1; - } + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + params->PchLockDownGlobalSmi = lockdown_by_fsp; + params->PchLockDownBiosInterface = lockdown_by_fsp; + params->PchUnlockGpioPads = !lockdown_by_fsp; + params->RtcMemoryLock = lockdown_by_fsp; /* coreboot will send EOP before loading payload */ params->EndOfPostMessage = EOP_DISABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/52844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Gerrit-Change-Number: 52844 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 13 Aug '21

13 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52843 ) Change subject: soc/intel/skylake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/skylake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-clause and adjust comments. This changes behavior since now related options are always set, depending on if coreboot or the FSP should be responsible for the chipset lockdown. This ensures a defined state independent from the default configuration of the FSP. Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52843 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/chip.c 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3979911..c99067d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -409,19 +409,19 @@ * do the changes and then lock it back in coreboot during finalize. */ tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - tconfig->PchLockDownBiosInterface = 0; - params->PchLockDownBiosLock = 0; - params->PchLockDownSpiEiss = 0; - /* - * Skip Spi Flash Lockdown from inside FSP. - * Making this config "0" means FSP won't set the FLOCKDN bit - * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). - * So, it becomes coreboot's responsibility to set this bit - * before end of POST for security concerns. - */ - params->SpiFlashCfgLockDown = 0; - } + + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + tconfig->PchLockDownBiosInterface = lockdown_by_fsp; + params->PchLockDownBiosLock = lockdown_by_fsp; + params->PchLockDownSpiEiss = lockdown_by_fsp; + /* + * Making this config "0" means FSP won't set the FLOCKDN bit + * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). + * So, it becomes coreboot's responsibility to set this bit + * before end of POST for security concerns. + */ + params->SpiFlashCfgLockDown = lockdown_by_fsp; + /* FSP should let coreboot set subsystem IDs, which are read/write-once */ params->DefaultSvid = 0; params->PchSubSystemVendorId = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/52843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Gerrit-Change-Number: 52843 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration
by Tim Wawrzynczak (Code Review) 13 Aug '21

13 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52842 ) Change subject: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/cannonlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause and adjust comments. Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52842 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 12 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 4a88458..2c82c38 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -642,35 +642,20 @@ #endif /* Chipset Lockdown */ - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - tconfig->PchLockDownGlobalSmi = 0; - tconfig->PchLockDownBiosInterface = 0; - params->PchLockDownBiosLock = 0; - params->PchLockDownRtcMemoryLock = 0; + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + tconfig->PchLockDownGlobalSmi = lockdown_by_fsp; + tconfig->PchLockDownBiosInterface = lockdown_by_fsp; + params->PchLockDownBiosLock = lockdown_by_fsp; + params->PchLockDownRtcMemoryLock = lockdown_by_fsp; #if CONFIG(SOC_INTEL_COMETLAKE) - /* - * Skip SPI Flash Lockdown from inside FSP. - * Making this config "0" means FSP won't set the FLOCKDN bit - * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). - * So, it becomes coreboot's responsibility to set this bit - * before end of POST for security concerns. - */ - params->SpiFlashCfgLockDown = 0; + /* + * Making this config "0" means FSP won't set the FLOCKDN bit + * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). + * So, it becomes coreboot's responsibility to set this bit + * before end of POST for security concerns. + */ + params->SpiFlashCfgLockDown = lockdown_by_fsp; #endif - } else { - tconfig->PchLockDownGlobalSmi = 1; - tconfig->PchLockDownBiosInterface = 1; - params->PchLockDownBiosLock = 1; - params->PchLockDownRtcMemoryLock = 1; -#if CONFIG(SOC_INTEL_COMETLAKE) - /* - * Enable SPI Flash Lockdown from inside FSP. - * Making this config "1" means FSP will set the FLOCKDN bit - * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). - */ - params->SpiFlashCfgLockDown = 1; -#endif - } #if !CONFIG(SOC_INTEL_COMETLAKE) params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign; -- To view, visit https://review.coreboot.org/c/coreboot/+/52842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Gerrit-Change-Number: 52842 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add TGL-H PCI IDs
by Tim Wawrzynczak (Code Review) 13 Aug '21

13 Aug '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56900 ) Change subject: soc/intel/common: Add TGL-H PCI IDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Gerrit-Change-Number: 56900 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 12 Aug 2021 21:39:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1
by Tim Wawrzynczak (Code Review) 13 Aug '21

13 Aug '21

Attention is currently required from: Furquan Shaikh, Caveh Jalali, Matthew Blecker, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56928 ) Change subject: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Thanks! Can you trigger submit? I'm not able to even with the CR+2. On coreboot.org, we usually let patches sit for at least 24 hours so folks all over the world are able to have a chance to review (go to https://doc.coreboot.org/getting_started/gerrit_guidelines.html?highlight=g… and find the line `Let non-trivial patches sit in a review state for at least 24 hours before submission.`). Someone will come along after that time and submit it. 😊 if it gets to be another day or two and it hasn't been yet, ping me and I can submit it. -- To view, visit https://review.coreboot.org/c/coreboot/+/56928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Gerrit-Change-Number: 56928 Gerrit-PatchSet: 5 Gerrit-Owner: Matthew Blecker <matthewb(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Matthew Blecker <matthewb(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 12 Aug 2021 20:01:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matthew Blecker <matthewb(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1
by Matthew Blecker (Code Review) 13 Aug '21

13 Aug '21

Attention is currently required from: Furquan Shaikh, Caveh Jalali, Paul Menzel. Matthew Blecker has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56928 ) Change subject: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Thanks! Can you trigger submit? I'm not able to even with the CR+2. -- To view, visit https://review.coreboot.org/c/coreboot/+/56928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Gerrit-Change-Number: 56928 Gerrit-PatchSet: 5 Gerrit-Owner: Matthew Blecker <matthewb(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 12 Aug 2021 19:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2021